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Merge remote-tracking branch 'origin/rebar-dev-align' into boom-add

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This commit is contained in:
abejgonzalez
2019-04-17 16:07:02 -07:00
parent 68b2da6b3a 7d887b212c
commit 80cbdd1d31
7 changed files with 24 additions and 41 deletions
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43
common.mk
View File

@@ -22,32 +22,12 @@ TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/class
######################################################################################### #########################################################################################
FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar FIRRTL_JAR ?= $(ROCKETCHIP_DIR)/lib/firrtl.jar
# this should match whatever the commonSettings version is in build.sbt
BARSTOOLS_VER=1.0
TAPEOUT_JAR=$(base_dir)/tools/barstools/tapeout/target/scala-$(SCALA_VERSION_MAJOR)/tapeout-assembly-$(BARSTOOLS_VER).jar
MACROCOMPILER_JAR=$(base_dir)/tools/barstools/macros/target/scala-$(SCALA_VERSION_MAJOR)/barstools-macros-assembly-$(BARSTOOLS_VER).jar
$(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala) $(FIRRTL_JAR): $(call lookup_scala_srcs, $(ROCKETCHIP_DIR)/firrtl/src/main/scala)
$(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala $(MAKE) -C $(ROCKETCHIP_DIR)/firrtl SBT="$(SBT)" root_dir=$(ROCKETCHIP_DIR)/firrtl build-scala
mkdir -p $(dir $@) mkdir -p $(dir $@)
cp -p $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar $@ cp -p $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar $@
touch $@ touch $@
$(TAPEOUT_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/tapeout/src/main/scala)
cd $(base_dir) && $(SBT) "tapeout/assembly"
$(MACROCOMPILER_JAR): $(call lookup_scala_srcs, $(base_dir)/tools/barstools/macros/src/main/scala) $(call lookup_scala_srcs, $(base_dir)/tools/barstools/mdf/scalalib/src/main/scala)
cd $(base_dir) && $(SBT) "barstools-macros/assembly"
.PHONY: jars
jars: $(MACROCOMPILER_JAR) $(TAPEOUT_JAR)
#########################################################################################
# tapeout and macrocompiler commands
#########################################################################################
TAPEOUT ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(TAPEOUT_JAR)
MACROCOMPILER ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(MACROCOMPILER_JAR)
######################################################################################### #########################################################################################
# create simulation args file rule # create simulation args file rule
######################################################################################### #########################################################################################
@@ -68,15 +48,18 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf)
######################################################################################### #########################################################################################
REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF)
$(VERILOG_FILE) $(SMEMS_CONF): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) $(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE)
$(TAPEOUT) barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) $(REPL_SEQ_MEM) -td $(build_dir) cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)"
cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes)
$(HARNESS_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) $(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes)
$(TAPEOUT) barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -td $(build_dir) cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)"
grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes)
# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
$(SMEMS_FILE): $(SMEMS_CONF) $(MACROCOMPILER_JAR) MACROCOMPILER_MODE ?= --mode synflops
$(MACROCOMPILER) barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) --mode synflops $(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF)
cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) $(MACROCOMPILER_MODE)"
######################################################################################### #########################################################################################
# helper rule to just make verilog files # helper rule to just make verilog files
@@ -139,11 +122,3 @@ regression-tests = \
run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests))) run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests)))
run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests))) run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests)))
run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests))) run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests)))
#########################################################################################
# general jar cleanup rule
#########################################################################################
.PHONY: clean-scala
clean-scala:
rm -rf $(MACROCOMPILER_JAR) $(TAPEOUT_JAR)

2
project/plugins.sbt
View File

@@ -1 +1,3 @@
addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.5") addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.5")
addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2")

4
sims/verisim/Makefile
View File

@@ -56,7 +56,7 @@ $(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
rm -rf $(build_dir)/$(long_name) rm -rf $(build_dir)/$(long_name)
mkdir -p $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \ $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
-o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \ -o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)" -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)"
touch $@ touch $@
@@ -64,7 +64,7 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
rm -rf $(build_dir)/$(long_name) rm -rf $(build_dir)/$(long_name)
mkdir -p $(build_dir)/$(long_name).debug mkdir -p $(build_dir)/$(long_name).debug
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \ $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \
-o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \ -o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)" -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)"
touch $@ touch $@

3
sims/vsim/Makefile
View File

@@ -55,7 +55,8 @@ VCS_NONCC_OPTS = \
+v2k \ +v2k \
+vcs+lic+wait \ +vcs+lic+wait \
+vc+list \ +vc+list \
-f $(sim_blackboxes) \ -f $(sim_top_blackboxes) \
-f $(sim_harness_blackboxes) \
-f $(sim_dotf) \ -f $(sim_dotf) \
-sverilog \ -sverilog \
+incdir+$(build_dir) \ +incdir+$(build_dir) \

1
src/main/scala/example/Simulator.scala
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@@ -82,6 +82,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
out.close() out.close()
} }
def resources(sim: Simulator): Seq[String] = Seq( def resources(sim: Simulator): Seq[String] = Seq(
"/testchipip/csrc/SimSerial.cc",
"/csrc/SimDTM.cc", "/csrc/SimDTM.cc",
"/csrc/SimJTAG.cc", "/csrc/SimJTAG.cc",
"/csrc/remote_bitbang.h", "/csrc/remote_bitbang.h",

2
tools/barstools

Submodule tools/barstools updated: 0b9d74ada7...e548210ef4

10
variables.mk
View File

@@ -35,10 +35,17 @@ long_name = $(PROJECT).$(MODEL).$(CONFIG)
FIRRTL_FILE ?= $(build_dir)/$(long_name).fir FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
ANNO_FILE ?= $(build_dir)/$(long_name).anno.json ANNO_FILE ?= $(build_dir)/$(long_name).anno.json
VERILOG_FILE ?= $(build_dir)/$(long_name).top.v VERILOG_FILE ?= $(build_dir)/$(long_name).top.v
TOP_FIR ?= $(build_dir)/$(long_name).top.fir
TOP_ANNO ?= $(build_dir)/$(long_name).top.anno.json
HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v
HARNESS_FIR ?= $(build_dir)/$(long_name).harness.fir
HARNESS_ANNO ?= $(build_dir)/$(long_name).harness.anno.json
SMEMS_FILE ?= $(build_dir)/$(long_name).mems.v SMEMS_FILE ?= $(build_dir)/$(long_name).mems.v
SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf
SMEMS_FIR ?= $(build_dir)/$(long_name).mems.fir
sim_dotf ?= $(build_dir)/sim_files.f sim_dotf ?= $(build_dir)/sim_files.f
sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f
######################################################################################### #########################################################################################
# default sbt launch command # default sbt launch command
@@ -66,9 +73,6 @@ rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
######################################################################################### #########################################################################################
# sources needed to run simulators # sources needed to run simulators
######################################################################################### #########################################################################################
sim_blackboxes = \
$(build_dir)/firrtl_black_box_resource_files.f
sim_vsrcs = \ sim_vsrcs = \
$(VERILOG_FILE) \ $(VERILOG_FILE) \
$(HARNESS_FILE) \ $(HARNESS_FILE) \