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Fix macrocompiler for RW mask port

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This commit is contained in:
Abraham Gonzalez
2019-10-25 20:42:55 -07:00
committed by GitHub
parent 26096e07f6
commit 7f0828cb30
1 changed files with 1 additions and 1 deletions
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2
macros/src/main/scala/MacroCompiler.scala
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@@ -511,7 +511,7 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
/* Palmer: If we don't have a chip enable but do have mask ports. */ /* Palmer: If we don't have a chip enable but do have mask ports. */
stmts += connectPorts(memMask, mask, mask_polarity) stmts += connectPorts(memMask, mask, mask_polarity)
stmts += connectPorts(andAddrMatch(and(memWriteEnable, memChipEnable)), stmts += connectPorts(andAddrMatch(and(memWriteEnable, memChipEnable)),
we, mask_polarity) we, we_polarity)
case (None, Some(PolarizedPort(we, we_polarity)), chipEnable) => case (None, Some(PolarizedPort(we, we_polarity)), chipEnable) =>
if (bitWidth(memMask.tpe) == 1) { if (bitWidth(memMask.tpe) == 1) {
/* Palmer: If we're expected to provide mask ports without a /* Palmer: If we're expected to provide mask ports without a