docs label disambiguation

2021-01-08 20:11:21 -08:00
parent 558cff7469
commit 7e092c655b
27 changed files with 72 additions and 69 deletions
--- a/docs/Generators/Rocket-Chip.rst
+++ b/docs/Generators/Rocket-Chip.rst
@@ -30,7 +30,7 @@ The tiles connect to the ``SystemBus``, which connect it to the L2 cache banks.
 The L2 cache banks then connect to the ``MemoryBus``, which connects to the
 DRAM controller through a TileLink to AXI converter.

-To learn more about the memory hierarchy, see :ref:`Memory Hierarchy`.
+To learn more about the memory hierarchy, see :ref:`Customization/Memory-Hierarchy:Memory Hierarchy`.

 MMIO
 ----