Update to chisel 3.2.x

build.sbt

@@ -39,6 +39,11 @@ lazy val macros = (project in file("macros"))
 
 lazy val tapeout = (project in file("tapeout"))
   .settings(commonSettings)
+  .settings(Seq(
+    libraryDependencies ++= Seq(
+      "io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0"
+    )
+  ))
   .settings(scalacOptions in Test ++= Seq("-language:reflectiveCalls"))
 
 lazy val root = (project in file(".")).aggregate(macros, tapeout)

tapeout/src/main/scala/transforms/.clkgen/ClkAnnotations.scala

@@ -92,7 +92,8 @@ abstract class FirrtlClkTransformAnnotation {
 }
 
 // Firrtl version
-case class TargetClkModAnnoF(target: ModuleName, anno: ClkModAnnotation) extends FirrtlClkTransformAnnotation {
+case class TargetClkModAnnoF(target: ModuleName, anno: ClkModAnnotation) extends FirrtlClkTransformAnnotation with SingleTargetAnnotation[ModuleName] {
+  def duplicate(n: ModuleName): TargetClkModAnnoF = this.copy(target = n)
   def getAnno = Annotation(target, classOf[ClkSrcTransform], anno.serialize)
   def targetName = target.name
   def modType = anno.modType
@@ -102,12 +103,13 @@ case class TargetClkModAnnoF(target: ModuleName, anno: ClkModAnnotation) extends
 }
 
 // Chisel version
-case class TargetClkModAnnoC(target: Module, anno: ClkModAnnotation) {
+case class TargetClkModAnnoC(target: Module, anno: ClkModAnnotation) extends ChiselAnnotation {
-  def getAnno = ChiselAnnotation(target, classOf[ClkSrcTransform], anno.serialize)
+  def toFirrtl = TargetClkModAnnoF(target.toNamed, anno)
 }
 
 // Firrtl version
-case class TargetClkPortAnnoF(target: ComponentName, anno: ClkPortAnnotation) extends FirrtlClkTransformAnnotation {
+case class TargetClkPortAnnoF(target: ComponentName, anno: ClkPortAnnotation) extends FirrtlClkTransformAnnotation with SingleTargetAnnotation[ComponentName] {
+  def duplicate(n: ComponentName): TargetClkPortAnnoF = this.copy(target = n)
   def getAnno = Annotation(target, classOf[ClkSrcTransform], anno.serialize)
   def targetName = Seq(target.module.name, target.name).mkString(".")
   def modId = Seq(target.module.name, anno.id).mkString(".")
@@ -115,8 +117,8 @@ case class TargetClkPortAnnoF(target: ComponentName, anno: ClkPortAnnotation) ex
 }
 
 // Chisel version
-case class TargetClkPortAnnoC(target: Element, anno: ClkPortAnnotation) {
+case class TargetClkPortAnnoC(target: Element, anno: ClkPortAnnotation) extends ChiselAnnotation {
-  def getAnno = ChiselAnnotation(target, classOf[ClkSrcTransform], anno.serialize)
+  def toFirrtl = TargetClkPortAnnoF(target.toNamed, anno)
 }
 
 object HasClkAnnotation {
@@ -170,9 +172,6 @@ trait IsClkModule {
 
   self: chisel3.Module =>
 
-  private def doNotDedup(module: Module): Unit = {
-    annotate(ChiselAnnotation(module, classOf[DedupModules], "nodedup!"))
-  }
   doNotDedup(this)
 
   private def extractElementNames(signal: Data): Seq[String] = {
@@ -212,7 +211,7 @@ trait IsClkModule {
     annotateDerivedClks(ClkModAnnotation(tpe.serialize, generatedClks))
   def annotateDerivedClks(anno: ClkModAnnotation): Unit = annotateDerivedClks(this, anno)
   def annotateDerivedClks(m: Module, anno: ClkModAnnotation): Unit =
-    annotate(TargetClkModAnnoC(m, anno).getAnno)
+    annotate(TargetClkModAnnoC(m, anno))
 
   def annotateClkPort(p: Element): Unit = annotateClkPort(p, None, "")
   def annotateClkPort(p: Element, sink: Sink): Unit = annotateClkPort(p, Some(sink), "")
@@ -229,12 +228,12 @@ trait IsClkModule {
   }
 
   def annotateClkPort(p: Element, anno: ClkPortAnnotation): Unit = {
-    p.dir match {
+    DataMirror.directionOf(p) match {
-      case chisel3.core.Direction.Input => 
+      case chisel3.core.ActualDirection.Input =>
         require(anno.tag.nonEmpty, "Module inputs must be clk sinks")
         require(anno.tag.get.src.isEmpty,
           "Clock module (not top) input clks should not have clk period, etc. specified")
-      case chisel3.core.Direction.Output =>
+      case chisel3.core.ActualDirection.Output =>
         require(anno.tag.isEmpty, "Module outputs must not be clk sinks (they're sources!)")
       case _ =>
         throw new Exception("Clk port direction must be specified!")
@@ -243,6 +242,6 @@ trait IsClkModule {
       case _: chisel3.core.Clock =>
       case _ => throw new Exception("Clock port must be of type Clock")
     }
-    annotate(TargetClkPortAnnoC(p, anno).getAnno)
+    annotate(TargetClkPortAnnoC(p, anno))
   }
 }

tapeout/src/main/scala/transforms/.pads/AddIOPadsTransform.scala

@@ -52,9 +52,9 @@ class AddIOPadsTransform extends Transform with SeqTransformBased {
         )
         // Expects BlackBox helper to be run after to inline pad Verilog!
         val ret = runTransforms(state)
-        val currentAnnos = ret.annotations.getOrElse(AnnotationMap(Seq.empty)).annotations
+        val currentAnnos = ret.annotations
-        val newAnnoMap = AnnotationMap(currentAnnos ++ bbAnnotations)
+        val newAnnoMap = AnnotationSeq(currentAnnos ++ bbAnnotations)
-        val newState = CircuitState(ret.circuit, outputForm, Some(newAnnoMap), ret.renames)
+        val newState = CircuitState(ret.circuit, outputForm, newAnnoMap, ret.renames)
 
         // TODO: *.f file is overwritten on subsequent executions, but it doesn't seem to be used anywhere?
         (new firrtl.transforms.BlackBoxSourceHelper).execute(newState)

tapeout/src/main/scala/transforms/.pads/AnnotateSupplyPads.scala

@@ -22,13 +22,13 @@ case class TopSupplyPad(
   require(pad.padType == SupplyPad)
 
   def padOrientation = padSide.orientation
-  def getPadName = pad.getName(NoDirection, padOrientation)
+  def getPadName = pad.getName(Output/*Should be None*/, padOrientation)
   def firrtlBBName = getPadName
   private def instNamePrefix = Seq(firrtlBBName, padSide.serialize).mkString("_")
   def instNames = (0 until num).map(i => Seq(instNamePrefix, i.toString).mkString("_"))
 
   def createPadInline(): String = {
-    def getPadVerilog(): String = pad.getVerilog(NoDirection, padOrientation)
+  def getPadVerilog(): String = pad.getVerilog(Output/*Should be None*/, padOrientation)
     s"""inline
       |${getPadName}.v
       |${getPadVerilog}""".stripMargin

tapeout/src/main/scala/transforms/.pads/ChiselTopModule.scala

@@ -20,11 +20,14 @@ abstract class TopModule(
     coreHeight: Int = 0,
     usePads: Boolean = true,
     override_clock: Option[Clock] = None,
-    override_reset: Option[Bool] = None) extends Module(override_clock, override_reset) with IsClkModule {
+    override_reset: Option[Bool] = None) extends Module with IsClkModule {
+
+    override_clock.foreach(clock := _)
+    override_reset.foreach(reset := _)
 
   override def annotateClkPort(p: Element, anno: ClkPortAnnotation): Unit = {
-    p.dir match {
+    DataMirror.directionOf(p) match {
-      case chisel3.core.Direction.Input => 
+      case chisel3.core.ActualDirection.Input =>
         require(anno.tag.nonEmpty, "Top Module input clks must be clk sinks")
         require(anno.tag.get.src.nonEmpty,
           "Top module input clks must have clk period, etc. specified")
@@ -35,7 +38,7 @@ abstract class TopModule(
       case _: chisel3.core.Clock =>
       case _ => throw new Exception("Clock port must be of type Clock")
     }
-    annotate(TargetClkPortAnnoC(p, anno).getAnno)
+    annotate(TargetClkPortAnnoC(p, anno))
   }
 
   override def annotateDerivedClks(m: Module, anno: ClkModAnnotation): Unit =
@@ -52,13 +55,13 @@ abstract class TopModule(
       coreHeight = coreHeight,
       supplyAnnos = supplyAnnos
     )
-    annotate(TargetModulePadAnnoC(this, modulePadAnnotation).getAnno)
+    annotate(TargetModulePadAnnoC(this, modulePadAnnotation))
   }
 
   // Annotate IO with side + pad name
   def annotatePad(sig: Element, side: PadSide = defaultPadSide, name: String = ""): Unit = if (usePads) {
     val anno = IOPadAnnotation(side.serialize, name)
-    annotate(TargetIOPadAnnoC(sig, anno).getAnno)
+    annotate(TargetIOPadAnnoC(sig, anno))
   }
   def annotatePad(sig: Aggregate, name: String): Unit = annotatePad(sig, side = defaultPadSide, name)
   def annotatePad(sig: Aggregate, side: PadSide): Unit = annotatePad(sig, side, name = "")
@@ -67,7 +70,7 @@ abstract class TopModule(
 
   // There may be cases where pads were inserted elsewhere. If that's the case, allow certain IO to
   // not have pads auto added. Note that annotatePad and noPad are mutually exclusive!
-  def noPad(sig: Element): Unit = if (usePads) annotate(TargetIOPadAnnoC(sig, NoIOPadAnnotation()).getAnno)
+  def noPad(sig: Element): Unit = if (usePads) annotate(TargetIOPadAnnoC(sig, NoIOPadAnnotation()))
   def noPad(sig: Aggregate): Unit = extractElements(sig) foreach { x => noPad(x) }
 
   // Since this is a super class, this should be the first thing that gets run

tapeout/src/main/scala/transforms/.pads/CreatePadBBs.scala

@@ -101,7 +101,7 @@ object CreatePadBBs {
     // Add annotations to black boxes to inline Verilog from template
     // Again, note the weirdness in parameterization -- just need to hook to one matching Firrtl instance
     val annos = uniqueParameterizedBBs.map(x =>
-      BlackBoxSourceAnnotation(ModuleName(x.firrtlBBName, CircuitName(c.main)), x.padInline)
+      BlackBoxInlineAnno(ModuleName(x.firrtlBBName, CircuitName(c.main)), x.firrtlBBName, x.padInline)
     ).toSeq
     (c.copy(modules = c.modules ++ bbs), annos)
   }

tapeout/src/main/scala/transforms/.pads/FoundryPadsYaml.scala

@@ -57,8 +57,8 @@ case class FoundryPad(
 
     private val orient = if (isHorizontal) Horizontal.serialize else Vertical.serialize
     private val dir = padType match {
-      case AnalogPad => InOut.serialize
+      case AnalogPad => "inout"
-      case SupplyPad => NoDirection.serialize
+      case SupplyPad => "none"
       case DigitalPad => if (isInput) Input.serialize else Output.serialize
     }
     val name = {

tapeout/src/main/scala/transforms/.pads/PadAnnotations.scala

@@ -34,13 +34,14 @@ case class NoIOPadAnnotation(noPad: String = "") extends IOAnnotation {
   def field = "noPad:"
 }
 // Firrtl version
-case class TargetIOPadAnnoF(target: ComponentName, anno: IOAnnotation) extends FirrtlPadTransformAnnotation {
+case class TargetIOPadAnnoF(target: ComponentName, anno: IOAnnotation) extends FirrtlPadTransformAnnotation with SingleTargetAnnotation[ComponentName] {
+  def duplicate(n: ComponentName): TargetIOPadAnnoF = this.copy(target = n)
   def getAnno = Annotation(target, classOf[AddIOPadsTransform], anno.serialize)
   def targetName = target.name
 }
 // Chisel version
-case class TargetIOPadAnnoC(target: Element, anno: IOAnnotation) {
+case class TargetIOPadAnnoC(target: Element, anno: IOAnnotation) extends ChiselAnnotation {
-  def getAnno = ChiselAnnotation(target, classOf[AddIOPadsTransform], anno.serialize)
+  def toFirrtl = TargetIOPadAnnoF(target.toNamed, anno)
 }
 
 // A bunch of supply pads (designated by name, # on each chip side) can be associated with the top module
@@ -63,13 +64,14 @@ case class ModulePadAnnotation(
   def getDefaultPadSide: PadSide = HasPadAnnotation.getSide(defaultPadSide)
 }
 // Firrtl version
-case class TargetModulePadAnnoF(target: ModuleName, anno: ModulePadAnnotation) extends FirrtlPadTransformAnnotation {
+case class TargetModulePadAnnoF(target: ModuleName, anno: ModulePadAnnotation) extends FirrtlPadTransformAnnotation with SingleTargetAnnotation[ModuleName] {
+  def duplicate(n: ModuleName): TargetModulePadAnnoF = this.copy(target = n)
   def getAnno = Annotation(target, classOf[AddIOPadsTransform], anno.serialize)
   def targetName = target.name
 }
 // Chisel version
-case class TargetModulePadAnnoC(target: Module, anno: ModulePadAnnotation) {
+case class TargetModulePadAnnoC(target: Module, anno: ModulePadAnnotation) extends ChiselAnnotation {
-  def getAnno = ChiselAnnotation(target, classOf[AddIOPadsTransform], anno.serialize)
+  def toFirrtl = TargetModulePadAnnoF(target.toNamed, anno)
 }
 
 case class CollectedAnnos(

tapeout/src/main/scala/transforms/.pads/PadDescriptors.scala

@@ -28,13 +28,6 @@ case object NoPad extends PadType {
   def serialize: String = "none"
 }
 
-case object InOut extends Direction {
-  def serialize: String = "inout"
-}
-case object NoDirection extends Direction {
-  def serialize: String = "none"
-}
-
 abstract class PadSide extends FirrtlNode {
   def orientation: PadOrientation
 }