Update to chisel 3.2.x

This commit is contained in:
Colin Schmidt
2020-02-18 14:56:17 -08:00
parent 5198b3883c
commit 7de4c478c3
9 changed files with 124 additions and 122 deletions

View File

@@ -7,11 +7,11 @@ import firrtl.ir._
import barstools.tapeout.transforms._
case class FoundryPad(
tpe: String,
name: String,
width: Int,
tpe: String,
name: String,
width: Int,
height: Int,
supplySetNum: Option[Int],
supplySetNum: Option[Int],
verilog: String) {
def padInstName = "PAD"
@@ -23,16 +23,16 @@ case class FoundryPad(
def getSupplySetNum = supplySetNum.getOrElse(1)
val padType = tpe match {
case "digital" =>
case "digital" =>
require(verilog.contains(DigitalPad.inName), "Digital pad template must contain input called 'in'")
require(verilog.contains(DigitalPad.outName), "Digital pad template must contain output called 'out'")
require(verilog.contains("{{#if isInput}}"), "Digital pad template must contain '{{#if isInput}}'")
DigitalPad
case "analog" =>
case "analog" =>
require(verilog.contains(AnalogPad.ioName), "Analog pad template must contain inout called 'io'")
require(!verilog.contains("{{#if isInput}}"), "Analog pad template must not contain '{{#if isInput}}'")
AnalogPad
case "supply" =>
case "supply" =>
// Supply pads don't have IO
require(!verilog.contains("{{#if isInput}}"), "Supply pad template must not contain '{{#if isInput}}'")
require(
@@ -57,8 +57,8 @@ case class FoundryPad(
private val orient = if (isHorizontal) Horizontal.serialize else Vertical.serialize
private val dir = padType match {
case AnalogPad => InOut.serialize
case SupplyPad => NoDirection.serialize
case AnalogPad => "inout"
case SupplyPad => "none"
case DigitalPad => if (isInput) Input.serialize else Output.serialize
}
val name = {
@@ -69,7 +69,7 @@ case class FoundryPad(
}
// Note: Analog + supply don't use direction
private def getTemplateParams(dir: Direction, orient: PadOrientation): TemplateParams =
private def getTemplateParams(dir: Direction, orient: PadOrientation): TemplateParams =
TemplateParams(isInput = (dir == Input), isHorizontal = (orient == Horizontal))
def getVerilog(dir: Direction, orient: PadOrientation): String = {
@@ -85,11 +85,11 @@ object FoundryPadsYaml extends DefaultYamlProtocol {
implicit val _pad = yamlFormat6(FoundryPad)
def parse(techDir: String): Seq[FoundryPad] = {
val file = techDir + exampleResource
if(techDir != "" && !(new java.io.File(file)).exists())
if(techDir != "" && !(new java.io.File(file)).exists())
throw new Exception("Technology directory must contain FoundryPads.yaml!")
val out = (new YamlFileReader(exampleResource)).parse[FoundryPad](if (techDir == "") "" else file)
val padNames = out.map(x => x.correctedName)
require(padNames.distinct.length == padNames.length, "Pad names must be unique!")
out
}
}
}