Update docs/Chipyard-Basics/Configs-Parameters-Mixins.rst [skip ci]

Co-Authored-By: Jerry Zhao <jerryz123@berkeley.edu>

docs/Chipyard-Basics/Configs-Parameters-Mixins.rst

@@ -103,7 +103,32 @@ implementation. The lazy module defines all the logical connections between
 generators and exchanges configuration information among them, while the
 module implementation performs the actual Chisel RTL elaboration.
 
-Mix-in
+In the MySoC example class, the "outer" ``MySoC`` instantiates the "inner" 
+``MySoCModuleImp`` as a lazy module. This delays immediate elaboration 
+of the module. The ``RocketSubsystem`` outer base class, as well as the 
+``HasPeripheryX`` outer traits contain code to perform high-level logical 
+connections. For example, the ``HasPeripherySerial`` outer trait contains code
+to lazily instantiate the ``SerialAdapter``, and connect the SerialAdapter's 
+TileLink node to the frontbus. 
+
+The ``ModuleImp`` classes and traits perform elaboration of real RTL.
+For example, the ``HasPeripherySerialModuleImp`` trait physically connects
+the ``SerialAdapter`` module, and instantiates queues. 
+
+In the test harness, the SoC is elaborated with 
+``val dut = Module(LazyModule(MySoC))``. 
+After elaboration, the result will be a MySoC module, which contains a
+SerialAdapter module (among others).
+
+From a high level, classes which extend LazyModule *must* reference 
+their module implementation through``lazy val module``, and they 
+*may* optionally reference other lazy modules (which will elaborate
+ as child modules in the module hierarchy). The "inner" modules 
+ contain the implementation for the module, and may instantiate 
+ other normal modules OR lazy modules (for nested Diplomacy 
+ graphs, for example. This is very advanced).
+ 
+ Mix-in
 ---------------------------
 
 A mix-in is a Scala trait, which sets parameters for specific system components, as well as enabling instantiation and wiring of the relevant system components to system buses.