wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

add optimizations

Browse Source
This commit is contained in:
Donggyu Kim
2017-07-26 00:15:08 -07:00
committed by edwardcwang
parent 9de1f5f2c0
commit 7cb5604dfa
2 changed files with 29 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
macros/src/main/scala/Utils.scala
View File

@@ -14,9 +14,9 @@ import scala.language.implicitConversions
class FirrtlMacroPort(port: MacroPort) {
val src = port
val isReader = !port.readEnable.isEmpty && port.writeEnable.isEmpty
val isWriter = !port.writeEnable.isEmpty && port.readEnable.isEmpty
val isReadWriter = !port.writeEnable.isEmpty && !port.readEnable.isEmpty
val isReader = port.output.nonEmpty && port.input.isEmpty
val isWriter = port.input.nonEmpty && port.output.isEmpty
val isReadWriter = port.input.nonEmpty && port.output.nonEmpty
val addrType = UIntType(IntWidth(ceilLog2(port.depth) max 1))
val dataType = UIntType(IntWidth(port.width))