Bump bringup VCU118 | Ignore HTIF if no-debug module

.gitmodules

@@ -133,4 +133,4 @@
 	url = https://github.com/ucb-bar/riscv-sodor.git
 [submodule "fpga/fpga-shells"]
 	path = fpga/fpga-shells
-	url = git@github.com:sifive/fpga-shells.git
+	url = git@github.com:abejgonzalez/fpga-shells.git

fpga/src/main/scala/vcu118/Configs.scala

@@ -28,7 +28,6 @@ class WithDefaultPeripherals extends Config((site, here, up) => {
 class WithSystemModifications extends Config((site, here, up) => {
   case BuildSystem => (p: Parameters) => new VCU118DigitalTop()(p) // use the VCU118-extended digital top
   case DebugModuleKey => None // disable debug module
-  case ExportDebug => up(ExportDebug).copy(protocols = Set(JTAG)) // don't generate HTIF DTS
   case SystemBusKey => up(SystemBusKey).copy(
     errorDevice = Some(DevNullParams(
       Seq(AddressSet(0x3000, 0xfff)),

fpga/src/main/scala/vcu118/bringup/Configs.scala

@@ -9,7 +9,6 @@ import freechips.rocketchip.diplomacy._
 
 import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams}
 import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams}
-import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 
 import sifive.fpgashells.shell.{DesignKey}
@@ -23,7 +22,6 @@ import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency, VCU118DDR2Size
 
 class WithBringupPeripherals extends Config((site, here, up) => {
   case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L)))
-  case PeripherySPIKey => up(PeripherySPIKey, site) ++ List(SPIParams(rAddress = BigInt(0x64004000L)))
   case PeripheryI2CKey => List(I2CParams(address = BigInt(0x64005000L)))
   case PeripheryGPIOKey => {
     if (BringupGPIOs.width > 0) {
@@ -38,12 +36,13 @@ class WithBringupPeripherals extends Config((site, here, up) => {
       List.empty[GPIOParams]
     }
   }
-  case TSIClockMaxFrequency => 100
+  case TSIClockMaxFrequencyKey => 100
   case PeripheryTSIHostKey => List(
     TSIHostParams(
       serialIfWidth = 4,
       mmioBaseAddress = BigInt(0x64006000),
       mmioSourceId = 1 << 13, // manager source
+      targetSize = site(VCU118DDR2Size),
       serdesParams = TSIHostSerdesParams(
         clientPortParams = TLMasterPortParameters.v1(
           clients = Seq(TLMasterParameters.v1(
@@ -51,7 +50,7 @@ class WithBringupPeripherals extends Config((site, here, up) => {
             sourceId = IdRange(0, (1 << 13))))),
         managerPortParams = TLSlavePortParameters.v1(
           managers = Seq(TLSlaveParameters.v1(
-            address = Seq(AddressSet(0, site(VCU118DDR2Size) - 1)),
+            address = Seq(AddressSet(0, BigInt("FFFFFFFF", 16))), // access everything on chip
             regionType = RegionType.UNCACHED,
             executable = true,
             supportsGet        = TransferSizes(1, 64),
@@ -71,7 +70,6 @@ class WithBringupVCU118System extends Config((site, here, up) => {
 
 class WithBringupAdditions extends Config(
   new WithBringupUART ++
-  new WithBringupSPI ++
   new WithBringupI2C ++
   new WithBringupGPIO ++
   new WithBringupTSIHost ++
@@ -87,7 +85,7 @@ class RocketBringupConfig extends Config(
   new chipyard.RocketConfig)
 
 class BoomBringupConfig extends Config(
-  new WithFPGAFrequency(75) ++
+  new WithFPGAFrequency(70) ++
   new WithBringupAdditions ++
   new WithVCU118Tweaks ++
   new chipyard.MegaBoomConfig)

fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala

@@ -69,46 +69,7 @@ class BringupUARTVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInp
   def place(designInput: UARTDesignInput) = new BringupUARTVCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
 }
 
-/* Connect SPI to ADI device */
+/* Connect GPIOs to FPGA I/Os */
-class BringupSPIVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: SPIDesignInput, val shellInput: SPIShellInput)
-   extends SDIOXilinxPlacedOverlay(name, designInput, shellInput)
-{
-  shell { InModuleBody {
-    val packagePinsWithPackageIOs = Seq((FMCPMap("H37"), IOPin(io.spi_clk)),
-                                        (FMCPMap("H19"), IOPin(io.spi_cs)),
-                                        (FMCPMap("H17"), IOPin(io.spi_dat(0))),
-                                        (FMCPMap("H28"), IOPin(io.spi_dat(1))),
-                                        (FMCPMap("H29"), IOPin(io.spi_dat(2))),
-                                        (FMCPMap("H16"), IOPin(io.spi_dat(3))))
-
-    packagePinsWithPackageIOs foreach { case (pin, io) => {
-      shell.xdc.addPackagePin(io, pin)
-      shell.xdc.addIOStandard(io, "LVCMOS18")
-    } }
-    packagePinsWithPackageIOs drop 1 foreach { case (pin, io) => {
-      shell.xdc.addPullup(io)
-      shell.xdc.addIOB(io)
-    } }
-  } }
-}
-
-class BringupSPIVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: SPIShellInput)(implicit val valName: ValName)
-  extends SPIShellPlacer[VCU118ShellBasicOverlays] {
-  def place(designInput: SPIDesignInput) = new BringupSPIVCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
-}
-
-// TODO: Move this to a different location
-// SPI device description for ADI part
-class ADISPIDevice(spi: Device, maxMHz: Double = 1) extends SimpleDevice("clkgen", Seq("analog,adi9516-4")) {
-  override def parent = Some(spi)
-  override def describe(resources: ResourceBindings): Description = {
-    val Description(name, mapping) = super.describe(resources)
-    val extra = Map("spi-max-frequency" -> Seq(ResourceInt(maxMHz * 1000000)))
-    Description(name, mapping ++ extra)
-  }
-}
-
-/* Connect GPIOs to FMC */
 abstract class GPIOXilinxPlacedOverlay(name: String, di: GPIODesignInput, si: GPIOShellInput)
   extends GPIOPlacedOverlay(name, di, si)
 {
@@ -192,7 +153,7 @@ class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name:
   }
 }
 
-case object TSIClockMaxFrequency extends Field[Int](50) // in MHz
+case object TSIClockMaxFrequencyKey extends Field[Int](50) // in MHz
 class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATestHarness, override val name: String, override val designInput: TSIHostDesignInput, override val shellInput: TSIHostShellInput)
   extends TSIHostVCU118PlacedOverlay(shell, name, designInput, shellInput)
 {
@@ -230,7 +191,7 @@ class BringupTSIHostVCU118PlacedOverlay(override val shell: BringupVCU118FPGATes
       shell.xdc.addIOB(io)
     } }
 
-    shell.sdc.addClock("TSI_CLK", clkIo, p(TSIClockMaxFrequency))
+    shell.sdc.addClock("TSI_CLK", clkIo, p(TSIClockMaxFrequencyKey))
     shell.sdc.addGroup(pins = Seq(clkIo))
     shell.xdc.clockDedicatedRouteFalse(clkIo)
   } }

fpga/src/main/scala/vcu118/bringup/DigitalTop.scala

@@ -10,8 +10,9 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 
 import chipyard.fpga.vcu118.{VCU118DigitalTop, VCU118DigitalTopModule}
+
 // ------------------------------------
-// BringupVCU118 DigitalTop
+// Bringup VCU118 DigitalTop
 // ------------------------------------
 
 class BringupVCU118DigitalTop(implicit p: Parameters) extends VCU118DigitalTop

fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala

@@ -27,17 +27,6 @@ class WithBringupUART extends ComposeHarnessBinder({
   }
 })
 
-/*** SPI ***/
-class WithBringupSPI extends ComposeHarnessBinder({
-  (system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => {
-    th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
-      require(ports.size == 2)
-
-      vcu118th.bringupOuter.io_adi_spi_bb.bundle <> ports.last
-    } }
-  }
-})
-
 /*** I2C ***/
 class WithBringupI2C extends OverrideHarnessBinder({
   (system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[I2CPort]) => {
@@ -79,5 +68,3 @@ class WithBringupTSIHost extends OverrideHarnessBinder({
     } }
   }
 })
-
-

fpga/src/main/scala/vcu118/bringup/TestHarness.scala

@@ -36,17 +36,6 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends
   val io_fmc_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last)))
   dp(UARTOverlayKey).last.place(UARTDesignInput(io_fmc_uart_bb))
 
-  /*** SPI ***/
-
-  require(dp(PeripherySPIKey).size == 2)
-
-  // 2nd SPI goes to the ADI port
-
-  val adi = Overlay(SPIOverlayKey, new BringupSPIVCU118ShellPlacer(this, SPIShellInput()))
-
-  val io_adi_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last)))
-  dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_adi_spi_bb))
-
   /*** I2C ***/
 
   val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput()))

generators/chipyard/src/main/scala/Subsystem.scala

@@ -11,7 +11,7 @@ import chisel3.internal.sourceinfo.{SourceInfo}
 import freechips.rocketchip.prci._
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.devices.tilelink._
-import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug}
+import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug, DebugModuleKey}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt}
 import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree}
@@ -31,7 +31,7 @@ trait CanHaveHTIF { this: BaseSubsystem =>
   // Advertise HTIF if system can communicate with fesvr
   if (this match {
     case _: CanHavePeripheryTLSerial if p(SerialTLKey).nonEmpty => true
-    case _: HasPeripheryDebug if p(ExportDebug).dmi => true
+    case _: HasPeripheryDebug if (!p(DebugModuleKey).isEmpty && p(ExportDebug).dmi) => true
     case _ => false
   }) {
     ResourceBinding {