diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
index 40f18d5d..021bd7ab 100644
--- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
@@ -1,8 +1,9 @@
 package chipyard.config
 
 import org.chipsalliance.cde.config.{Config}
-import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper}
+import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper, InclusiveCacheKey}
 import freechips.rocketchip.diplomacy.{DTSTimebase}
+import sifive.blocks.inclusivecache.{InclusiveCachePortParameters}
 
 // Replaces the L2 with a broadcast manager for maintaining coherence
 class WithBroadcastManager extends Config((site, here, up) => {
@@ -16,3 +17,9 @@ class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => {
 class WithDTSTimebase(freqMHz: BigInt) extends Config((site, here, up) => {
   case DTSTimebase => freqMHz
 })
+
+// Adds buffers on the interior of the inclusive L2, to improve PD
+class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
+  case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerInterior=buffer, bufOuterInterior=buffer)
+})
+