Add SPI flash support (#546)
* Add SPI flash configs, IOBinders, CI tests, and docs * Add writable SPI flash support * bump * Fix CI * Fix CI * Update docs/Generators/TestChipIP.rst Co-authored-by: Chick Markley <chick@qrhino.com> * Maybe actually fix CI * Fix broken merge * Fix the tutorial patch * bump tcip to master * fix GPIO naming bug Co-authored-by: Chick Markley <chick@qrhino.com>
This commit is contained in:
John Wright
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tests/spiflash.h
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174
tests/spiflash.h
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#ifndef __SPIFLASH_H__
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#define __SPIFLASH_H__
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// These are configuration-dependent, but for the unit test we'll use the example config
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#define SPIFLASH_BASE_MEM 0x20000000
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#define SPIFLASH_BASE_MEM_SIZE 0x10000000
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#define SPIFLASH_BASE_CTRL 0x10040000
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// Only defining the registers we use; there are more
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// Software control
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#define SPIFLASH_OFFS_CSMODE 0x18
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#define SPIFLASH_OFFS_FMT 0x40
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#define SPIFLASH_OFFS_TXDATA 0x48
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#define SPIFLASH_OFFS_RXDATA 0x4c
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// Hardware state machine control
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#define SPIFLASH_OFFS_FLASH_EN 0x60
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#define SPIFLASH_OFFS_FFMT 0x64
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// chip select modes
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#define CSMODE_AUTO 0
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#define CSMODE_HOLD 2
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#define CSMODE_OFF 3
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// SPI flash protocol settings
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#define SPIFLASH_PROTO_SINGLE 0
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#define SPIFLASH_PROTO_DUAL 1
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#define SPIFLASH_PROTO_QUAD 2
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// SPI flash IO settings
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#define SPIFLASH_IODIR_RX 0
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#define SPIFLASH_IODIR_TX 1
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// SPI flash endianness settings
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#define SPIFLASH_ENDIAN_MSB 0
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#define SPIFLASH_ENDIAN_LSB 1
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static uint8_t test_data[] = {0x13,0x37,0x00,0xff,0xaa,0x55,0xfa,0xce,0x0f,0xf0,0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef};
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static uint8_t test_len = 16;
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typedef union
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{
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struct {
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unsigned int proto : 2;
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unsigned int endian : 1;
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unsigned int iodir : 1;
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unsigned int : 12;
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unsigned int len : 4;
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unsigned int : 12;
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} fields;
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uint32_t bits;
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} spi_fmt;
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typedef union
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{
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struct {
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unsigned int cmd_en : 1;
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unsigned int addr_len : 3;
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unsigned int pad_cnt : 4;
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unsigned int cmd_proto : 2;
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unsigned int addr_proto : 2;
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unsigned int data_proto : 2;
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unsigned int : 2;
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unsigned int cmd_code : 8;
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unsigned int pad_code : 8;
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} fields;
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uint32_t bits;
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} spiflash_ffmt;
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// send something to the SPI TX
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void spi_data_write(uint8_t data)
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{
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while (reg_read32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_TXDATA) >= 0x80000000);
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reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_TXDATA, (uint32_t)data);
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}
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// configure the hardware flash controller
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void configure_spiflash(spiflash_ffmt data)
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{
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reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 0);
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reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FFMT, data.bits);
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reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 1);
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}
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// write some data to the flash using software (there is no hardware write controller)
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void write_spiflash(uint8_t *data, uint32_t len, uint32_t addr, uint8_t cmd, uint8_t abytes, uint8_t aproto, uint8_t dproto)
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{
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spi_fmt fmt;
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fmt.fields.proto = SPIFLASH_PROTO_SINGLE;
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fmt.fields.endian = SPIFLASH_ENDIAN_MSB;
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fmt.fields.iodir = SPIFLASH_IODIR_TX;
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fmt.fields.len = 8;
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uint32_t i;
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// Need to be out of flash mode
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reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 0);
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reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FMT, fmt.bits);
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reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_CSMODE, CSMODE_HOLD);
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spi_data_write(cmd);
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// need to wait a bit to flush the tx queue before changing fmt
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for(i = 0; i < 0x100; i++) asm volatile ("nop");
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fmt.fields.proto = aproto;
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reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FMT, fmt.bits);
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for (i = abytes; i > 0; i--)
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{
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spi_data_write((uint8_t)(addr >> (i*8-8)));
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}
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// need to wait a bit to flush the tx queue before changing fmt
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for(i = 0; i < 0x100; i++) asm volatile ("nop");
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fmt.fields.proto = dproto;
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reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FMT, fmt.bits);
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for (i = 0; i < len; i++)
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{
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spi_data_write(data[i]);
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}
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// need to wait a bit to flush the tx queue before deasserting CS
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for(i = 0; i < 0x100; i++) asm volatile ("nop");
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reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_CSMODE, CSMODE_OFF);
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// go back into flash read mode
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reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 1);
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}
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// test that a large chunk of memory contains (0xdeadbeef - address) or 0
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int test_spiflash(uint32_t start, uint32_t size, uint8_t zero)
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{
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uint32_t i;
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for (i = start; i < (start + size); i += 4)
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{
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uint32_t data = reg_read32(SPIFLASH_BASE_MEM + i);
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uint32_t check = 0;
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if (!zero) check = 0xdeadbeef - i;
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if(data != check)
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{
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printf("Error reading address 0x%08x from SPI flash. Got 0x%08x, expected 0x%08x.\n", i, data, check);
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return 1;
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}
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}
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return 0;
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}
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// this is a variant of test_spiflash that only tests a small array of values
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int check_write(uint8_t *check, uint32_t len, uint32_t addr)
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{
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uint32_t i;
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for (i = 0; i < len; i += 4)
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{
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uint32_t data = reg_read32(SPIFLASH_BASE_MEM + addr + i);
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uint32_t check32 = ((uint32_t *)check)[i/4];
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if(check32 != data)
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{
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printf("Error reading address 0x%08x from SPI flash. Got 0x%02x, expected 0x%02x.\n", i + addr, data, check32);
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return 1;
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}
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}
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return 0;
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}
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#endif /* __SPIFLASH_H__ */
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