Add SPI flash support (#546)

* Add SPI flash configs, IOBinders, CI tests, and docs * Add writable SPI flash support * bump * Fix CI * Fix CI * Update docs/Generators/TestChipIP.rst Co-authored-by: Chick Markley <chick@qrhino.com> * Maybe actually fix CI * Fix broken merge * Fix the tutorial patch * bump tcip to master * fix GPIO naming bug Co-authored-by: Chick Markley <chick@qrhino.com>
2020-05-14 19:19:50 -07:00
parent 1b1f477619
commit 7c7b336c3f
18 changed files with 505 additions and 16 deletions
--- a/tests/.gitignore
+++ b/tests/.gitignore
@@ -1,4 +1,5 @@
 *.o
 *.riscv
 *.dump
+*.img
 libgloss/
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -5,12 +5,15 @@ LDFLAGS= -static

 include libgloss.mk

-PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd
+PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd spiflashread spiflashwrite
+
+spiflash.img: spiflash.py
+	python3 $<

 .DEFAULT_GOAL := default

 .PHONY: default
-default: $(addsuffix .riscv,$(PROGRAMS))
+default: $(addsuffix .riscv,$(PROGRAMS)) spiflash.img

 .PHONY: dumps
 dumps: $(addsuffix .dump,$(PROGRAMS))
@@ -18,7 +21,7 @@ dumps: $(addsuffix .dump,$(PROGRAMS))
 %.o: %.S
 	$(GCC) $(CFLAGS) -D__ASSEMBLY__=1 -c $< -o $@

-%.o: %.c mmio.h
+%.o: %.c mmio.h spiflash.h
 	$(GCC) $(CFLAGS) -c $< -o $@

 %.riscv: %.o $(libgloss)
--- a/tests/spiflash.h
+++ b/tests/spiflash.h
@@ -0,0 +1,174 @@
+#ifndef __SPIFLASH_H__
+#define __SPIFLASH_H__
+
+// These are configuration-dependent, but for the unit test we'll use the example config
+#define SPIFLASH_BASE_MEM 0x20000000
+#define SPIFLASH_BASE_MEM_SIZE 0x10000000
+
+#define SPIFLASH_BASE_CTRL 0x10040000
+// Only defining the registers we use; there are more
+// Software control
+#define SPIFLASH_OFFS_CSMODE 0x18
+#define SPIFLASH_OFFS_FMT 0x40
+#define SPIFLASH_OFFS_TXDATA 0x48
+#define SPIFLASH_OFFS_RXDATA 0x4c
+// Hardware state machine control
+#define SPIFLASH_OFFS_FLASH_EN 0x60
+#define SPIFLASH_OFFS_FFMT 0x64
+
+// chip select modes
+#define CSMODE_AUTO 0
+#define CSMODE_HOLD 2
+#define CSMODE_OFF 3
+
+// SPI flash protocol settings
+#define SPIFLASH_PROTO_SINGLE 0
+#define SPIFLASH_PROTO_DUAL 1
+#define SPIFLASH_PROTO_QUAD 2
+
+// SPI flash IO settings
+#define SPIFLASH_IODIR_RX 0
+#define SPIFLASH_IODIR_TX 1
+
+// SPI flash endianness settings
+#define SPIFLASH_ENDIAN_MSB 0
+#define SPIFLASH_ENDIAN_LSB 1
+
+static uint8_t test_data[] = {0x13,0x37,0x00,0xff,0xaa,0x55,0xfa,0xce,0x0f,0xf0,0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef};
+static uint8_t test_len = 16;
+
+typedef union
+{
+	struct {
+		unsigned int proto : 2;
+		unsigned int endian : 1;
+		unsigned int iodir : 1;
+		unsigned int : 12;
+		unsigned int len : 4;
+		unsigned int : 12;
+	} fields;
+	uint32_t bits;
+} spi_fmt;
+
+typedef union
+{
+	struct {
+		unsigned int cmd_en : 1;
+		unsigned int addr_len : 3;
+		unsigned int pad_cnt : 4;
+		unsigned int cmd_proto : 2;
+		unsigned int addr_proto : 2;
+		unsigned int data_proto : 2;
+		unsigned int : 2;
+		unsigned int cmd_code : 8;
+		unsigned int pad_code : 8;
+	} fields;
+	uint32_t bits;
+} spiflash_ffmt;
+
+// send something to the SPI TX
+void spi_data_write(uint8_t data)
+{
+	while (reg_read32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_TXDATA) >= 0x80000000);
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_TXDATA, (uint32_t)data);
+}
+
+// configure the hardware flash controller
+void configure_spiflash(spiflash_ffmt data)
+{
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 0);
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FFMT, data.bits);
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 1);
+}
+
+// write some data to the flash using software (there is no hardware write controller)
+void write_spiflash(uint8_t *data, uint32_t len, uint32_t addr, uint8_t cmd, uint8_t abytes, uint8_t aproto, uint8_t dproto)
+{
+
+	spi_fmt fmt;
+	fmt.fields.proto = SPIFLASH_PROTO_SINGLE;
+	fmt.fields.endian = SPIFLASH_ENDIAN_MSB;
+	fmt.fields.iodir = SPIFLASH_IODIR_TX;
+	fmt.fields.len = 8;
+
+	uint32_t i;
+
+	// Need to be out of flash mode
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 0);
+
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FMT, fmt.bits);
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_CSMODE, CSMODE_HOLD);
+
+	spi_data_write(cmd);
+
+	// need to wait a bit to flush the tx queue before changing fmt
+	for(i = 0; i < 0x100; i++) asm volatile ("nop");
+
+	fmt.fields.proto = aproto;
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FMT, fmt.bits);
+
+	for (i = abytes; i > 0; i--)
+	{
+		spi_data_write((uint8_t)(addr >> (i*8-8)));
+	}
+
+	// need to wait a bit to flush the tx queue before changing fmt
+	for(i = 0; i < 0x100; i++) asm volatile ("nop");
+
+	fmt.fields.proto = dproto;
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FMT, fmt.bits);
+
+	for (i = 0; i < len; i++)
+	{
+		spi_data_write(data[i]);
+	}
+
+	// need to wait a bit to flush the tx queue before deasserting CS
+	for(i = 0; i < 0x100; i++) asm volatile ("nop");
+
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_CSMODE, CSMODE_OFF);
+
+	// go back into flash read mode
+	reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 1);
+
+}
+
+// test that a large chunk of memory contains (0xdeadbeef - address) or 0
+int test_spiflash(uint32_t start, uint32_t size, uint8_t zero)
+{
+	uint32_t i;
+
+	for (i = start; i < (start + size); i += 4)
+	{
+		uint32_t data = reg_read32(SPIFLASH_BASE_MEM + i);
+		uint32_t check = 0;
+		if (!zero) check = 0xdeadbeef - i;
+		if(data != check)
+		{
+			printf("Error reading address 0x%08x from SPI flash. Got 0x%08x, expected 0x%08x.\n", i, data, check);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+// this is a variant of test_spiflash that only tests a small array of values
+int check_write(uint8_t *check, uint32_t len, uint32_t addr)
+{
+	uint32_t i;
+	for (i = 0; i < len; i += 4)
+	{
+		uint32_t data = reg_read32(SPIFLASH_BASE_MEM + addr + i);
+		uint32_t check32 = ((uint32_t *)check)[i/4];
+		if(check32 != data)
+		{
+			printf("Error reading address 0x%08x from SPI flash. Got 0x%02x, expected 0x%02x.\n", i + addr, data, check32);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+#endif /* __SPIFLASH_H__ */
--- a/tests/spiflash.py
+++ b/tests/spiflash.py
@@ -0,0 +1,11 @@
+#!/usr/bin/env python3
+
+# Generates a binary file that the SPI test uses
+
+outfile = "spiflash.img"
+
+with open(outfile, 'wb') as f:
+    for i in range(0,0x100000,4):
+        check = 0xdeadbeef - i
+        f.write(check.to_bytes(4,'little'))
+
--- a/tests/spiflashread.c
+++ b/tests/spiflashread.c
@@ -0,0 +1,77 @@
+#include <stdlib.h>
+#include <stdio.h>
+
+#include "mmio.h"
+#include "spiflash.h"
+
+int main(void)
+{
+	spiflash_ffmt ffmt;
+	ffmt.fields.cmd_en = 1;
+	ffmt.fields.addr_len = 4; // Valid options are 3 or 4 for our model
+	ffmt.fields.pad_cnt = 0; // Our SPI flash model assumes 8 dummy cycles for fast reads, 0 for slow
+	ffmt.fields.cmd_proto = SPIFLASH_PROTO_SINGLE; // Our SPI flash model only supports single-bit commands
+	ffmt.fields.addr_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad
+	ffmt.fields.data_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad
+	ffmt.fields.cmd_code = 0x13; // Slow read 4 byte
+	ffmt.fields.pad_code = 0x00; // Not used by our model
+
+	printf("Testing SPI flash command 0x13...\n");
+	configure_spiflash(ffmt);
+	if (test_spiflash(0x0, 0x100, 0)) return 1;
+
+	printf("Testing SPI flash command 0x03...\n");
+	ffmt.fields.cmd_code = 0x03; // Slow read 3 byte address
+	ffmt.fields.addr_len = 3; // 3 byte address
+	configure_spiflash(ffmt);
+	if (test_spiflash(0x0, 0x100, 0)) return 1;
+
+	printf("Testing SPI flash command 0x0B...\n");
+	ffmt.fields.cmd_code = 0x0B; // Fast read 3 byte address
+	ffmt.fields.pad_cnt = 8; // Needs to be 8 for fast read
+	configure_spiflash(ffmt);
+	if (test_spiflash(0x1000, 0x100, 0)) return 1;
+
+	printf("Testing SPI flash command 0x0C...\n");
+	ffmt.fields.cmd_code = 0x0C; // Fast read 4 byte address
+	ffmt.fields.addr_len = 4; // 4 byte address
+	configure_spiflash(ffmt);
+	if (test_spiflash(0x2340, 0x100, 0)) return 1;
+
+	printf("Testing SPI flash command 0x6C...\n");
+	ffmt.fields.cmd_code = 0x6C; // Fast read 4 byte address, quad data
+	ffmt.fields.data_proto = SPIFLASH_PROTO_QUAD; // Quad data
+	configure_spiflash(ffmt);
+	if (test_spiflash(0x410c, 0x100, 0)) return 1;
+
+	printf("Testing SPI flash command 0x6B...\n");
+	ffmt.fields.cmd_code = 0x6B; // Fast read 3 byte address, quad data
+	ffmt.fields.addr_len = 3;
+	configure_spiflash(ffmt);
+	if (test_spiflash(0x5ff8, 0x100, 0)) return 1;
+
+	printf("Testing SPI flash command 0xEB...\n");
+	ffmt.fields.cmd_code = 0xEB; // Fast read 3 byte address, quad data, quad addr
+	ffmt.fields.addr_proto = SPIFLASH_PROTO_QUAD;
+	configure_spiflash(ffmt);
+	if (test_spiflash(0x7c04, 0x100, 0)) return 1;
+
+	printf("Testing SPI flash command 0xEC...\n");
+	ffmt.fields.cmd_code = 0xEC; // Fast read 4 byte address, quad data, quad addr
+	ffmt.fields.addr_len = 4;
+	configure_spiflash(ffmt);
+	if (test_spiflash(0x9000, 0x100, 0)) return 1;
+
+	printf("Testing SPI flash extended range...\n");
+	// The provided memory image is only 1MiB, but the model has 16MiB of addressable space
+	// This should return 0
+	if (test_spiflash(0x100000, 0x100, 1)) return 1;
+
+	// This write should do nothing, so we can just re-test the first test
+	printf("Testing that the SPI is not writable...\n");
+	write_spiflash(test_data, test_len, 0x0, 0x3E, 4, SPIFLASH_PROTO_QUAD, SPIFLASH_PROTO_QUAD);
+	if (test_spiflash(0x0, 0x100, 0)) return 1;
+
+	return 0;
+
+}
--- a/tests/spiflashwrite.c
+++ b/tests/spiflashwrite.c
@@ -0,0 +1,55 @@
+#include <stdlib.h>
+#include <stdio.h>
+
+#include "mmio.h"
+#include "spiflash.h"
+
+int main(void)
+{
+	spiflash_ffmt ffmt;
+	ffmt.fields.cmd_en = 1;
+	ffmt.fields.addr_len = 4; // Valid options are 3 or 4 for our model
+	ffmt.fields.pad_cnt = 0; // Our SPI flash model assumes 8 dummy cycles for fast reads, 0 for slow
+	ffmt.fields.cmd_proto = SPIFLASH_PROTO_SINGLE; // Our SPI flash model only supports single-bit commands
+	ffmt.fields.addr_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad
+	ffmt.fields.data_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad
+	ffmt.fields.cmd_code = 0x13; // Slow read 4 byte
+	ffmt.fields.pad_code = 0x00; // Not used by our model
+
+	// Test that we can read
+	printf("Testing SPI flash command 0x13...\n");
+	configure_spiflash(ffmt);
+	if (test_spiflash(0x0, 0x100, 0)) return 1;
+
+	// 0x02: 3 byte addr, single/single
+	printf("Testing SPI flash command 0x02...\n");
+	write_spiflash(test_data, test_len, 0x200, 0x02, 3, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_SINGLE);
+	if (check_write(test_data, test_len, 0x200)) return 1;
+
+	// 0x32: 3 byte addr, single/quad
+	printf("Testing SPI flash command 0x32...\n");
+	write_spiflash(test_data, test_len, 0x300, 0x32, 3, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_QUAD);
+	if (check_write(test_data, test_len, 0x300)) return 1;
+
+	// 0x38: 3 byte addr, quad/quad
+	printf("Testing SPI flash command 0x38...\n");
+	write_spiflash(test_data, test_len, 0x400, 0x38, 3, SPIFLASH_PROTO_QUAD, SPIFLASH_PROTO_QUAD);
+	if (check_write(test_data, test_len, 0x400)) return 1;
+
+	// 0x12: 4 byte addr, single/single
+	printf("Testing SPI flash command 0x12...\n");
+	write_spiflash(test_data, test_len, 0x500, 0x12, 4, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_SINGLE);
+	if (check_write(test_data, test_len, 0x500)) return 1;
+
+	// 0x34: 4 byte addr, single/quad
+	printf("Testing SPI flash command 0x34...\n");
+	write_spiflash(test_data, test_len, 0x600, 0x34, 4, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_QUAD);
+	if (check_write(test_data, test_len, 0x600)) return 1;
+
+	// 0x3E: 4 byte addr, quad/quad
+	printf("Testing SPI flash command 0x3E...\n");
+	write_spiflash(test_data, test_len, 0x700, 0x3E, 4, SPIFLASH_PROTO_QUAD, SPIFLASH_PROTO_QUAD);
+	if (check_write(test_data, test_len, 0x700)) return 1;
+
+	return 0;
+}