Rename cache/blocks submodules to match new chipsalliance ownership

This commit is contained in:
Jerry Zhao
2024-01-04 14:09:54 -08:00
parent d9bc036cb6
commit 7c13574769
15 changed files with 37 additions and 37 deletions

View File

@@ -1,8 +1,8 @@
Rocket Chip
===========
Rocket Chip generator is an SoC generator developed at Berkeley and now supported by
`SiFive <https://www.sifive.com>`__. Chipyard uses the Rocket Chip generator as the basis for producing a RISC-V SoC.
Rocket Chip generator is an SoC generator developed at Berkeley and SiFive, and now maintained openly in Chips Alliance.
Chipyard uses the Rocket Chip generator as the basis for producing a RISC-V SoC.
`Rocket Chip` is distinct from `Rocket core`, the in-order RISC-V CPU generator.
Rocket Chip includes many parts of the SoC besides the CPU. Though Rocket Chip