Rename cache/blocks submodules to match new chipsalliance ownership

2024-01-04 14:09:54 -08:00
parent d9bc036cb6
commit 7c13574769
15 changed files with 37 additions and 37 deletions
--- a/docs/Customization/Custom-Chisel.rst
+++ b/docs/Customization/Custom-Chisel.rst
@@ -59,7 +59,7 @@ should look something like this:
 .. code-block:: scala

    lazy val chipyard = (project in file("generators/chipyard"))
-        .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
+        .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
            sha3, dsptools, `rocket-dsp-utils`,
            gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
            yourproject, // <- added to the middle of the list for simplicity