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Rename cache/blocks submodules to match new chipsalliance ownership

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This commit is contained in:
Jerry Zhao
2024-01-04 14:09:54 -08:00
parent d9bc036cb6
commit 7c13574769
15 changed files with 37 additions and 37 deletions
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docs/Chipyard-Basics/Chipyard-Components.rst
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@@ -53,9 +53,9 @@ System Components:
**icenet**
A Network Interface Controller (NIC) designed to achieve up to 200 Gbps.
**sifive-blocks**
System components implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket Chip generator.
These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices.
**rocket-chip-blocks**
System components originally implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket Chip generator.
Now maintained by Chips Alliance. These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices.
**AWL (Analog Widget Library)**
Digital components required for integration with high speed serial links.