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Bump rocketchip | fix tracegen intnode

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This commit is contained in:
Jerry Zhao
2023-03-31 18:07:36 -07:00
parent 60bd1209cf
commit 7bfeef6459
2 changed files with 3 additions and 3 deletions
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2
generators/rocket-chip

Submodule generators/rocket-chip updated: c49644ecdd...02dba8e340

4
generators/tracegen/src/main/scala/System.scala
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@@ -3,7 +3,7 @@ package tracegen
import chisel3._ import chisel3._
import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple, NullIntSyncSource} import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple, NullIntSyncSource, IntSyncXbar}
import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile} import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile}
import freechips.rocketchip.subsystem._ import freechips.rocketchip.subsystem._
import boom.lsu.BoomTraceGenTile import boom.lsu.BoomTraceGenTile
@@ -17,7 +17,7 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
case t: GroundTestTile => t.statusNode.makeSink() case t: GroundTestTile => t.statusNode.makeSink()
case t: BoomTraceGenTile => t.statusNode.makeSink() case t: BoomTraceGenTile => t.statusNode.makeSink()
} }
val debugNode = NullIntSyncSource() lazy val debugNode = IntSyncXbar() := NullIntSyncSource()
override lazy val module = new TraceGenSystemModuleImp(this) override lazy val module = new TraceGenSystemModuleImp(this)
} }