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Fix IOCell generation for clock and reset to use IOCellKey

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This commit is contained in:
Kartik Prabhu
2021-03-10 16:50:36 -08:00
parent d98d6d1875
commit 7bcfaf1b7d
1 changed files with 3 additions and 2 deletions
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5
generators/chipyard/src/main/scala/Clocks.scala
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@@ -14,6 +14,7 @@ import barstools.iocell.chisel._
import testchipip.{TLTileResetCtrl} import testchipip.{TLTileResetCtrl}
import chipyard.clocking._ import chipyard.clocking._
import chipyard.iobinders._
/** /**
* A simple reset implementation that punches out reset ports * A simple reset implementation that punches out reset ports
@@ -25,7 +26,7 @@ object GenerateReset {
implicit val p = chiptop.p implicit val p = chiptop.p
// this needs directionality so generateIOFromSignal works // this needs directionality so generateIOFromSignal works
val async_reset_wire = Wire(Input(AsyncReset())) val async_reset_wire = Wire(Input(AsyncReset()))
val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(async_reset_wire, "reset", val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(async_reset_wire, "reset", p(IOCellKey),
abstractResetAsAsync = true) abstractResetAsAsync = true)
chiptop.iocells ++= resetIOCell chiptop.iocells ++= resetIOCell
@@ -94,7 +95,7 @@ object ClockingSchemeGenerators {
InModuleBody { InModuleBody {
val clock_wire = Wire(Input(Clock())) val clock_wire = Wire(Input(Clock()))
val reset_wire = GenerateReset(chiptop, clock_wire) val reset_wire = GenerateReset(chiptop, clock_wire)
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock") val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
chiptop.iocells ++= clockIOCell chiptop.iocells ++= clockIOCell
referenceClockSource.out.unzip._1.map { o => referenceClockSource.out.unzip._1.map { o =>