wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

[firechip] Rework FireSim clocking to be more similar to default CY targets

Browse Source
This commit is contained in:
David Biancolin
2020-09-24 23:32:07 -07:00
parent cc949aadab
commit 7b8a954d04
4 changed files with 96 additions and 105 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
generators/firechip/src/main/scala/BridgeBinders.scala
View File

@@ -68,9 +68,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
class WithSerialBridge extends OverrideHarnessBinder({
(system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
ports.map { p =>
withClockAndReset(p.clock, th.harnessReset) {
SerialBridge(p.clock, p.bits, MainMemoryConsts.globalName)(GetSystemParameters(system))
}
SerialBridge(p.clock, p.bits, MainMemoryConsts.globalName)(GetSystemParameters(system))
}
Nil
}
@@ -79,7 +77,7 @@ class WithSerialBridge extends OverrideHarnessBinder({
class WithNICBridge extends OverrideHarnessBinder({
(system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => {
val p: Parameters = GetSystemParameters(system)
ports.map { n => withClockAndReset(n.clock, th.harnessReset) { NICBridge(n.clock, n.bits)(p) } }
ports.map { n => NICBridge(n.clock, n.bits)(p) }
Nil
}
})
@@ -119,11 +117,7 @@ class WithFASEDBridge extends OverrideHarnessBinder({
class WithTracerVBridge extends ComposeHarnessBinder({
(system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[TraceOutputTop]) => {
ports.map { p =>
p.traces.map(
tileTrace => withClockAndReset(tileTrace.clock, tileTrace.reset) { TracerVBridge(tileTrace)(system.p) }
)
}
ports.map { p => p.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p)) }
Nil
}
})