Rework simulation splash page

docs/Simulation/FPGA-Accelerated-Simulators.rst

@@ -1,4 +1,4 @@
-FPGA-Based Simulators
+FPGA-Accelerated Simulators
 ==============================
 
 FireSim

docs/Simulation/Open-Source-Simulators.rst

@@ -1,35 +0,0 @@
-Open Source Software RTL Simulators
-===================================
-
-Verilator
------------------------
-
-`Verilator <https://www.veripool.org/wiki/verilator>`__ is an open-source LGPL-Licensed simulator maintained by `Veripool <https://www.veripool.org/>`__.
-The Chipyard framework can download, build, and execute simulations using Verilator.
-
-To run a simulation using Verilator, perform the following steps:
-
-To compile the example design, run ``make`` in the ``sims/verisim`` directory.
-This will elaborate the ``DefaultRocketConfig`` in the example project.
-
-An executable called ``simulator-example-DefaultRocketConfig`` will be produced.
-This executable is a simulator that has been compiled based on the design that was built.
-You can then use this executable to run any compatible RV64 code.
-For instance, to run one of the riscv-tools assembly tests.
-
-.. code-block:: shell
-
-    ./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
-
-If you later create your own project, you can use environment variables to build an alternate configuration.
-
-.. code-block:: shell
-
-    make SUB_PROJECT=yourproject
-    ./simulator-<yourproject>-<yourconfig> ...
-
-If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``.
-This will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer.
-An open-source vcd-capable waveform viewer is `GTKWave <http://gtkwave.sourceforge.net/>`__.
-
-Please refer to :ref:`Running A Simulation` for a step by step tutorial on how to get a simulator up and running.

docs/Simulation/SW-RTL-Simulators.rst

@@ -1,9 +1,43 @@
-Commercial Software RTL Simulators
+Software RTL Simulators
-==================================
+===================================
 
-VCS
+Verilator (Open-Source)
 -----------------------
 
+`Verilator <https://www.veripool.org/wiki/verilator>`__ is an open-source LGPL-Licensed simulator maintained by `Veripool <https://www.veripool.org/>`__.
+The Chipyard framework can download, build, and execute simulations using Verilator.
+
+To run a simulation using Verilator, perform the following steps:
+
+To compile the example design, run ``make`` in the ``sims/verisim`` directory.
+This will elaborate the ``DefaultRocketConfig`` in the example project.
+
+An executable called ``simulator-example-DefaultRocketConfig`` will be produced.
+This executable is a simulator that has been compiled based on the design that was built.
+You can then use this executable to run any compatible RV64 code.
+For instance, to run one of the riscv-tools assembly tests.
+
+.. code-block:: shell
+
+    ./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
+
+If you later create your own project, you can use environment variables to build an alternate configuration.
+
+.. code-block:: shell
+
+    make SUB_PROJECT=yourproject
+    ./simulator-<yourproject>-<yourconfig> ...
+
+If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``.
+This will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer.
+An open-source vcd-capable waveform viewer is `GTKWave <http://gtkwave.sourceforge.net/>`__.
+
+Please refer to :ref:`Running A Simulation` for a step by step tutorial on how to get a simulator up and running.
+Commercial Software RTL Simulators
+
+Synopsys VCS (License Required)
+--------------------------------
+
 `VCS <https://www.synopsys.com/verification/simulation/vcs.html>`__ is a commercial RTL simulator developed by Synopsys.
 It requires commercial licenses.
 The Chipyard framework can compile and execute simulations using VCS.

docs/Simulation/index.rst

@@ -1,15 +1,20 @@
 Simulators
 =======================
 
-Chipyard provides support and integration for multiple simulation flows, for various user levels and requirements.
+Chipyard supports two classes of simulation:
-In the majority of cases during a digital design development process, a simple software RTL simulation will do.
+
-When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution.
+#. Software RTL simulation using commercial or open-source (Verilator) RTL simulators 
-The following pages provide detailed information about the simulation possibilities within the Chipyard framework.
+#. FPGA-accelerated full-system simulation using FireSim
+
+Software RTL simulators of Chipyard designs run at O(1 KHz), but compile
+quickly and provide full waveforms. Conversly, FPGA-accelerated simulators run
+at O(100 MHz), making them appropriate for booting an operating system and
+running a complete workload, but have long compile time and poorer debug
+visability.
 
 .. toctree::
    :maxdepth: 2
    :caption: Simulators:
 
-   Open-Source-Simulators
+   SW-RTL-Simulators
-   Commercial-Simulators
+   FPGA-Accelerated-Simulators
-   FPGA-Based-Simulators