From 7b05dd199d3e6ebdfacf4163d0823a1eea019e0b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 12 Jun 2023 16:26:00 -0700 Subject: [PATCH] Prefetching config should use non-blocking L1D$ --- generators/bar-fetchers | 2 +- generators/chipyard/src/main/scala/config/RocketConfigs.scala | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/generators/bar-fetchers b/generators/bar-fetchers index e1a16ff9..3a33d818 160000 --- a/generators/bar-fetchers +++ b/generators/bar-fetchers @@ -1 +1 @@ -Subproject commit e1a16ff9834aafe805ec4a113b7dd5ce7ddd905b +Subproject commit 3a33d818aefe5444aa27fc1557008f747538d2cc diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 1c3884bc..95c2cbae 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -130,7 +130,8 @@ class CustomIOChipTopRocketConfig extends Config( class PrefetchingRocketConfig extends Config( new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++ // strided prefetcher, sits in front of the L1D$, monitors core requests to prefetching into the L1D$ new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++ // next-line prefetcher, sits between L1I$ and L2, monitors L1I$ misses to prefetch into L2 - new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher, site between L1D$ and L2, monitors L1D$ misses to prefetch into L2 + new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher, sits between L1D$ and L2, monitors L1D$ misses to prefetch into L2 new chipyard.config.WithTilePrefetchers ++ // add TL prefetchers between tiles and the sbus + new freechips.rocketchip.subsystem.WithNonblockingL1(2) ++ // non-blocking L1D$, L1 prefetching only works with non-blocking L1D$ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig)