From 7ae43a1829cb16515402772e25b06fc16b1fbebd Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 12 May 2023 10:51:34 -0700 Subject: [PATCH] Fix tracegenconfig --- .../chipyard/src/main/scala/config/TracegenConfigs.scala | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index 3818f551..20286fd6 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -11,14 +11,17 @@ class AbstractTraceGenConfig extends Config( new chipyard.iobinders.WithAXI4MemPunchthrough ++ new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++ new chipyard.clocking.WithPassthroughClockGenerator ++ + new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "implicit"))) ++ new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ - new chipyard.config.WithMemoryBusFrequency(100.0) ++ - new chipyard.config.WithPeripheryBusFrequency(100.0) ++ + new chipyard.config.WithMemoryBusFrequency(1000.0) ++ + new chipyard.config.WithSystemBusFrequency(1000.0) ++ + new chipyard.config.WithPeripheryBusFrequency(1000.0) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.groundtest.GroundTestBaseConfig) + class TraceGenConfig extends Config( new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ new AbstractTraceGenConfig)