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split RocketConfigs into RoCCAccelConfigs and MMIOAccelConfigs

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This commit is contained in:
Jerry Zhao
2023-02-11 12:44:42 -08:00
parent f2dfd295e2
commit 7a8bbd0747
3 changed files with 104 additions and 81 deletions
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58
generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala Normal file
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@@ -0,0 +1,58 @@
package chipyard
import freechips.rocketchip.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// ------------------------------
// Configs with MMIO accelerators
// ------------------------------
// DOC include start: FFTRocketConfig
class FFTRocketConfig extends Config(
new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include end: FFTRocketConfig
// DOC include start: GCDTLRocketConfig
class GCDTLRocketConfig extends Config(
new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++ // Use GCD Chisel, connect Tilelink
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include end: GCDTLRocketConfig
// DOC include start: GCDAXI4BlackBoxRocketConfig
class GCDAXI4BlackBoxRocketConfig extends Config(
new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++ // Use GCD blackboxed verilog, connect by AXI4->Tilelink
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include end: GCDAXI4BlackBoxRocketConfig
// DOC include start: InitZeroRocketConfig
class InitZeroRocketConfig extends Config(
new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++ // add InitZero
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include end: InitZeroRocketConfig
class StreamingPassthroughRocketConfig extends Config(
new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include start: StreamingFIRRocketConfig
class StreamingFIRRocketConfig extends Config (
new chipyard.example.WithStreamingFIR ++ // use top with tilelink-controlled streaming FIR
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include end: StreamingFIRRocketConfig
class SmallNVDLARocketConfig extends Config(
new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
class LargeNVDLARocketConfig extends Config(
new nvidia.blocks.dla.WithNVDLA("large", true) ++ // add a large NVDLA with synth. rams
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

46
generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala Normal file
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@@ -0,0 +1,46 @@
package chipyard
import freechips.rocketchip.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
// ------------------------------
// Configs with RoCC Accelerators
// ------------------------------
// DOC include start: GemminiRocketConfig
class GemminiRocketConfig extends Config(
new gemmini.DefaultGemminiConfig ++ // use Gemmini systolic array GEMM accelerator
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
// DOC include end: GemminiRocketConfig
class FPGemminiRocketConfig extends Config(
new gemmini.GemminiFP32DefaultConfig ++ // use FP32Gemmini systolic array GEMM accelerator
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class HwachaRocketConfig extends Config(
new chipyard.config.WithHwachaTest ++
new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
class MempressRocketConfig extends Config(
new mempress.WithMemPress ++ // use Mempress (memory traffic generation) accelerator
new chipyard.config.WithExtMemIdBits(7) ++ // use 7 bits for tl like request id
new chipyard.config.WithSystemBusWidth(128) ++
new freechips.rocketchip.subsystem.WithNBanks(8) ++
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=16, capacityKB=2048) ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
class HwachaLargeBoomConfig extends Config(
new chipyard.config.WithHwachaTest ++
new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
new boom.common.WithNLargeBooms(1) ++
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)

81
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -21,45 +21,6 @@ class TinyRocketConfig extends Config(
new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)
class MempressRocketConfig extends Config(
new mempress.WithMemPress ++ // use Mempress (memory traffic generation) accelerator
new freechips.rocketchip.subsystem.WithNBanks(8) ++
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=16, capacityKB=2048) ++
new chipyard.config.WithExtMemIdBits(7) ++ // use 7 bits for tl like request id
new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++
new chipyard.config.WithSystemBusWidth(128) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include start: FFTRocketConfig
class FFTRocketConfig extends Config(
new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include end: FFTRocketConfig
class HwachaRocketConfig extends Config(
new chipyard.config.WithHwachaTest ++
new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
// DOC include start: GemminiRocketConfig
class GemminiRocketConfig extends Config(
new gemmini.DefaultGemminiConfig ++ // use Gemmini systolic array GEMM accelerator
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
// DOC include end: GemminiRocketConfig
class FPGemminiRocketConfig extends Config(
new gemmini.GemminiFP32DefaultConfig ++ // use FP32Gemmini systolic array GEMM accelerator
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.WithSystemBusWidth(128) ++
new chipyard.config.AbstractConfig)
// DOC include start: DmiRocket // DOC include start: DmiRocket
class dmiRocketConfig extends Config( class dmiRocketConfig extends Config(
new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial
@@ -68,19 +29,6 @@ class dmiRocketConfig extends Config(
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)
// DOC include end: DmiRocket // DOC include end: DmiRocket
// DOC include start: GCDTLRocketConfig
class GCDTLRocketConfig extends Config(
new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++ // Use GCD Chisel, connect Tilelink
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include end: GCDTLRocketConfig
// DOC include start: GCDAXI4BlackBoxRocketConfig
class GCDAXI4BlackBoxRocketConfig extends Config(
new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++ // Use GCD blackboxed verilog, connect by AXI4->Tilelink
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include end: GCDAXI4BlackBoxRocketConfig
class LargeSPIFlashROMRocketConfig extends Config( class LargeSPIFlashROMRocketConfig extends Config(
new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only) new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only)
@@ -137,13 +85,6 @@ class GB1MemoryRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)
// DOC include start: InitZeroRocketConfig
class InitZeroRocketConfig extends Config(
new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++ // add InitZero
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include end: InitZeroRocketConfig
class LoopbackNICRocketConfig extends Config( class LoopbackNICRocketConfig extends Config(
new chipyard.harness.WithLoopbackNIC ++ // drive NIC IOs with loopback new chipyard.harness.WithLoopbackNIC ++ // drive NIC IOs with loopback
new icenet.WithIceNIC ++ // add an IceNIC new icenet.WithIceNIC ++ // add an IceNIC
@@ -188,28 +129,6 @@ class RingSystemBusRocketConfig extends Config(
new chipyard.config.AbstractConfig) new chipyard.config.AbstractConfig)
// DOC include end: RingSystemBusRocket // DOC include end: RingSystemBusRocket
class StreamingPassthroughRocketConfig extends Config(
new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include start: StreamingFIRRocketConfig
class StreamingFIRRocketConfig extends Config (
new chipyard.example.WithStreamingFIR ++ // use top with tilelink-controlled streaming FIR
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include end: StreamingFIRRocketConfig
class SmallNVDLARocketConfig extends Config(
new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
class LargeNVDLARocketConfig extends Config(
new nvidia.blocks.dla.WithNVDLA("large", true) ++ // add a large NVDLA with synth. rams
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
class MMIORocketConfig extends Config( class MMIORocketConfig extends Config(
new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port
new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port