wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Bump to support firesim simulation of no-AXI4DRAM designs

Browse Source
This commit is contained in:
Jerry Zhao
2020-10-01 10:21:43 -07:00
parent 164617e2d6
commit 79042e4ce8
2 changed files with 6 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
generators/firechip/src/main/scala/BridgeBinders.scala
View File

@@ -9,7 +9,7 @@ import freechips.rocketchip.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp} import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.amba.axi4.{AXI4Bundle} import freechips.rocketchip.amba.axi4.{AXI4Bundle}
import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp} import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp, ExtMem}
import freechips.rocketchip.tile.{RocketTile} import freechips.rocketchip.tile.{RocketTile}
import sifive.blocks.devices.uart._ import sifive.blocks.devices.uart._
@@ -67,9 +67,10 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
class WithSerialBridge extends OverrideHarnessBinder({ class WithSerialBridge extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => { (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
ports.map { p => ports.map { port =>
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, p, th.harnessReset) implicit val p = GetSystemParameters(system)
SerialBridge(p.clock, ram.module.io.tsi_ser, MainMemoryConsts.globalName)(GetSystemParameters(system)) val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset)
SerialBridge(port.clock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName))
} }
Nil Nil
} }

2
sims/firesim

Submodule sims/firesim updated: 801baeb901...ef615d35da