Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip

generators/chipyard/src/main/scala/HarnessBinders.scala

@@ -234,7 +234,14 @@ class WithTieOffInterrupts extends OverrideHarnessBinder({
 
 class WithTieOffL2FBusAXI extends OverrideHarnessBinder({
   (system: CanHaveSlaveAXI4Port, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[AXI4Bundle]]) => {
-    ports.foreach({ p => p := DontCare; p.bits.tieoff() })
+    ports.foreach({ p =>
+      p.bits := DontCare
+      p.bits.aw.valid := false.B
+      p.bits.w.valid := false.B
+      p.bits.b.ready := false.B
+      p.bits.ar.valid := false.B
+      p.bits.r.ready := false.B
+    })
   }
 })
 
@@ -274,7 +281,10 @@ class WithTiedOffDebug extends OverrideHarnessBinder({
         d.dmiClock := false.B.asClock
         d.dmiReset := true.B
       case a: ClockedAPBBundle =>
-        a.tieoff()
+        a.pready := false.B
+        a.pslverr := false.B
+        a.prdata := 0.U
+        a.pduser := DontCare
         a.clock := false.B.asClock
         a.reset := true.B.asAsyncReset
         a.psel := false.B

generators/chipyard/src/main/scala/IOBinders.scala

@@ -287,7 +287,7 @@ class WithAXI4MemPunchthrough extends OverrideLazyIOBinder({
         p.clock := clockBundle.clock
         p.reset := clockBundle.reset
         p
-      })
+      }).toSeq
       (ports, Nil)
     }
   }
@@ -307,7 +307,7 @@ class WithAXI4MMIOPunchthrough extends OverrideLazyIOBinder({
         p.clock := clockBundle.clock
         p.reset := clockBundle.reset
         p
-      })
+      }).toSeq
       (ports, Nil)
     }
   }
@@ -326,7 +326,7 @@ class WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({
         m <> p.bits
         p.clock := clockBundle.clock
         p
-      })
+      }).toSeq
       (ports, Nil)
     }
   }

generators/chipyard/src/main/scala/TestSuites.scala

@@ -74,11 +74,15 @@ class TestSuiteHelper
           addSuites(env.map(rv32uf))
           if (cfg.fLen >= 64)
             addSuites(env.map(rv32ud))
+          if (cfg.minFLen <= 16)
+            addSuites(env.map(rv32uzfh))
         } else {
           addSuite(rv32udBenchmarks)
           addSuites(env.map(rv64uf))
           if (cfg.fLen >= 64)
             addSuites(env.map(rv64ud))
+          if (cfg.minFLen <= 16)
+            addSuites(env.map(rv64uzfh))
         }
       }
       if (coreParams.useAtomics) {

generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala

@@ -119,7 +119,8 @@ case class DividerOnlyClockGeneratorNode(pllName: String)(implicit valName: ValN
 class DividerOnlyClockGenerator(pllName: String)(implicit p: Parameters, valName: ValName) extends LazyModule {
   val node = DividerOnlyClockGeneratorNode(pllName)
 
-  lazy val module = new LazyRawModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyRawModuleImp(this) {
     require(node.out.size == 1, "Idealized PLL expects to generate a single output clock group. Use a ClockGroupAggregator")
     val (refClock, ClockEdgeParameters(_, refSinkParam, _, _)) = node.in.head
     val (outClocks, ClockGroupEdgeParameters(_, outSinkParams,  _, _)) = node.out.head

generators/chipyard/src/main/scala/clocking/TileResetSetter.scala

@@ -34,7 +34,7 @@ class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], i
       }
     })
     tlNode.regmap((0 until nTiles).map({ i =>
-      i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io)),
+      i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io))
     }): _*)
 
     val tileMap = tileNames.zipWithIndex.map({ case (n, i) =>

generators/chipyard/src/main/scala/config/fragments/TileFragments.scala

@@ -25,7 +25,7 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
 class WithTraceIO extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      trace = true))
+      core = tp.tileParams.core.copy(trace = true)))
     case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       trace = true))
     case other => other
@@ -36,7 +36,7 @@ class WithTraceIO extends Config((site, here, up) => {
 class WithNoTraceIO extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
-      trace = false))
+      core = tp.tileParams.core.copy(trace = false)))
     case tp: CVA6TileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       trace = false))
     case other => other

generators/chipyard/src/main/scala/example/TutorialTile.scala

@@ -62,6 +62,11 @@ case class MyCoreParams(
   val decodeWidth: Int = 1 // TODO: Check
   val fetchWidth: Int = 1 // TODO: Check
   val retireWidth: Int = 2
+  val useBitManip: Boolean = false
+  val useBitManipCrypto: Boolean = false
+  val useCryptoNIST: Boolean = false
+  val useCryptoSM: Boolean = false
+  val traceHasWdata: Boolean = false
 }
 
 // DOC include start: CanAttachTile

generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala

@@ -40,7 +40,7 @@ class AddDefaultTests extends Phase with HasRocketChipStageUtils {
       // If a custom test suite is set up, use the custom test suite
       annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p))
 
-    RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations
+    RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations.toSeq
   }
 
 

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -76,7 +76,7 @@ class WithSerialBridge extends OverrideHarnessBinder({
       val ram = withClockAndReset(th.buildtopClock, th.buildtopReset) {
         SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset)
       }
-      SerialBridge(th.buildtopClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName))
+      SerialBridge(th.buildtopClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName), th.buildtopReset.asBool)
     }
     Nil
   }
@@ -97,7 +97,7 @@ class WithUARTBridge extends OverrideHarnessBinder({
     val pbusClockNode = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(PBUS).fixedClockNode
     val pbusClock = pbusClockNode.in.head._1.clock
     BoringUtils.bore(pbusClock, Seq(uartSyncClock))
-    ports.map { p => UARTBridge(uartSyncClock, p)(system.p) }; Nil
+    ports.map { p => UARTBridge(uartSyncClock, p, th.buildtopReset.asBool)(system.p) }; Nil
 })
 
 class WithBlockDeviceBridge extends OverrideHarnessBinder({
@@ -134,7 +134,7 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({
             axiClockBundle,
             th.buildtopReset)
         }
-        SerialBridge(th.buildtopClock, harnessMultiClockAXIRAM.module.io.tsi_ser, Some(MainMemoryConsts.globalName))
+        SerialBridge(th.buildtopClock, harnessMultiClockAXIRAM.module.io.tsi_ser, Some(MainMemoryConsts.globalName), th.buildtopReset.asBool)
 
         // connect SimAxiMem
         (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi4, edge) =>