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Merge pull request #1467 from ucb-bar/jerryz123-patch-2

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Generate objdump | check BINARY | cospike fixes
This commit is contained in:
Jerry Zhao
2023-05-17 16:07:11 -07:00
committed by GitHub
parent 4f33c2dddc abf2af16b4
commit 76cf492bdf
2 changed files with 25 additions and 12 deletions
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8
common.mk
View File

@@ -292,6 +292,11 @@ check-binary:
ifeq (,$(BINARY)) ifeq (,$(BINARY))
$(error BINARY variable is not set. Set it to the simulation binary) $(error BINARY variable is not set. Set it to the simulation binary)
endif endif
ifneq (none,$(BINARY))
ifeq ("$(wildcard $(BINARY))","")
$(error BINARY=$(BINARY) not found)
endif
endif
# allow you to override sim prereq # allow you to override sim prereq
ifeq (,$(BREAK_SIM_PREREQ)) ifeq (,$(BREAK_SIM_PREREQ))
@@ -309,6 +314,9 @@ run-binary-fast: $(SIM_PREREQ) check-binary | $(output_dir)
# run simulator with as much debug info as possible # run simulator with as much debug info as possible
run-binary-debug: $(SIM_DEBUG_PREREQ) check-binary | $(output_dir) run-binary-debug: $(SIM_DEBUG_PREREQ) check-binary | $(output_dir)
ifneq (none,$(BINARY))
riscv64-unknown-elf-objdump -D $(BINARY) > $(sim_out_name).dump
endif
(set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) </dev/null 2> >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) (set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) </dev/null 2> >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log)
run-fast: run-asm-tests-fast run-bmark-tests-fast run-fast: run-asm-tests-fast run-bmark-tests-fast

29
generators/chipyard/src/main/resources/csrc/cospike.cc
View File

@@ -63,7 +63,8 @@ extern "C" void cospike_set_sysinfo(char* isa, int pmpregions,
) { ) {
if (!info) { if (!info) {
info = new system_info_t; info = new system_info_t;
info->isa = std::string(isa); // technically the targets aren't zicntr compliant, but they implement the zicntr registers
info->isa = std::string(isa) + "_zicntr";
info->pmpregions = pmpregions; info->pmpregions = pmpregions;
info->mem0_base = mem0_base; info->mem0_base = mem0_base;
info->mem0_size = mem0_size; info->mem0_size = mem0_size;
@@ -266,12 +267,15 @@ extern "C" void cospike_cosim(long long int cycle,
#endif #endif
uint64_t s_pc = s->pc; uint64_t s_pc = s->pc;
uint64_t interrupt_cause = cause & 0x7FFFFFFFFFFFFFFF; uint64_t interrupt_cause = cause & 0x7FFFFFFFFFFFFFFF;
bool ssip_interrupt = interrupt_cause == 0x1;
bool msip_interrupt = interrupt_cause == 0x3; bool msip_interrupt = interrupt_cause == 0x3;
bool debug_interrupt = interrupt_cause == 0xe; bool debug_interrupt = interrupt_cause == 0xe;
if (raise_interrupt) { if (raise_interrupt) {
printf("%d interrupt %lx\n", cycle, cause); printf("%d interrupt %lx\n", cycle, cause);
if (msip_interrupt) { if (ssip_interrupt) {
// do nothing
} else if (msip_interrupt) {
s->mip->backdoor_write_with_mask(MIP_MSIP, MIP_MSIP); s->mip->backdoor_write_with_mask(MIP_MSIP, MIP_MSIP);
} else if (debug_interrupt) { } else if (debug_interrupt) {
return; return;
@@ -284,9 +288,9 @@ extern "C" void cospike_cosim(long long int cycle,
printf("%d exception %lx\n", cycle, cause); printf("%d exception %lx\n", cycle, cause);
if (valid) { if (valid) {
printf("%d Cosim: %lx", cycle, iaddr); printf("%d Cosim: %lx", cycle, iaddr);
if (has_wdata) { // if (has_wdata) {
printf(" s: %lx", wdata); // printf(" s: %lx", wdata);
} // }
printf("\n"); printf("\n");
} }
if (valid || raise_interrupt || raise_exception) { if (valid || raise_interrupt || raise_exception) {
@@ -299,7 +303,7 @@ extern "C" void cospike_cosim(long long int cycle,
} }
} }
if (valid) { if (valid && !raise_exception) {
if (s_pc != iaddr) { if (s_pc != iaddr) {
printf("%d PC mismatch spike %llx != DUT %llx\n", cycle, s_pc, iaddr); printf("%d PC mismatch spike %llx != DUT %llx\n", cycle, s_pc, iaddr);
if (unlikely(cospike_debug)) { if (unlikely(cospike_debug)) {
@@ -373,12 +377,13 @@ extern "C" void cospike_cosim(long long int cycle,
bool csr_read = (insn & 0x7f) == 0x73; bool csr_read = (insn & 0x7f) == 0x73;
if (csr_read) if (csr_read)
printf("CSR read %lx\n", csr_addr); printf("CSR read %lx\n", csr_addr);
if (csr_read && ((csr_addr == 0xf13) || // mimpid if (csr_read && ((csr_addr == 0xf13) || // mimpid
(csr_addr == 0xf12) || // marchid (csr_addr == 0xf12) || // marchid
(csr_addr == 0xf11) || // mvendorid (csr_addr == 0xf11) || // mvendorid
(csr_addr == 0xb00) || // mcycle (csr_addr == 0xb00) || // mcycle
(csr_addr == 0xb02) || // minstret (csr_addr == 0xb02) || // minstret
(csr_addr >= 0x3b0 && csr_addr <= 0x3ef) // pmpaddr (csr_addr >= 0x7a0 && csr_addr <= 0x7aa) || // debug trigger registers
(csr_addr >= 0x3b0 && csr_addr <= 0x3ef) // pmpaddr
)) { )) {
printf("CSR override\n"); printf("CSR override\n");
s->XPR.write(rd, wdata); s->XPR.write(rd, wdata);