Move src/ from tapeout to top level
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270
src/test/scala/mdf/macrolib/MacroLibOutput.scala
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270
src/test/scala/mdf/macrolib/MacroLibOutput.scala
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package mdf.macrolib
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import org.scalatest.flatspec.AnyFlatSpec
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import org.scalatest.matchers.should.Matchers
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import play.api.libs.json._
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import java.io.File
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// Output tests (Scala -> JSON).
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// TODO: unify these tests with the input tests?
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trait HasAwesomeMemData {
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def getAwesomeMem() = {
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SRAMMacro(
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name = "awesome_mem",
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width = 32,
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depth = 1024,
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family = "1rw",
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ports = Seq(
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MacroPort(
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address = PolarizedPort(name = "addr", polarity = ActiveHigh),
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clock = Some(PolarizedPort(name = "clk", polarity = PositiveEdge)),
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writeEnable = Some(PolarizedPort(name = "write_enable", polarity = ActiveHigh)),
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readEnable = Some(PolarizedPort(name = "read_enable", polarity = ActiveHigh)),
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chipEnable = Some(PolarizedPort(name = "chip_enable", polarity = ActiveHigh)),
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output = Some(PolarizedPort(name = "data_out", polarity = ActiveHigh)),
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input = Some(PolarizedPort(name = "data_in", polarity = ActiveHigh)),
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maskPort = Some(PolarizedPort(name = "mask", polarity = ActiveHigh)),
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maskGran = Some(8),
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width = Some(32),
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depth = Some(1024) // These numbers don't matter.
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)
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),
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extraPorts = List()
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)
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}
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def getAwesomeMemJSON(): String = {
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"""
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| {
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| "type": "sram",
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| "name": "awesome_mem",
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| "width": 32,
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| "depth": "1024",
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| "mux": 1,
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| "mask":true,
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| "family": "1rw",
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| "ports": [
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| {
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| "address port name": "addr",
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| "address port polarity": "active high",
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| "clock port name": "clk",
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| "clock port polarity": "positive edge",
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| "write enable port name": "write_enable",
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| "write enable port polarity": "active high",
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| "read enable port name": "read_enable",
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| "read enable port polarity": "active high",
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| "chip enable port name": "chip_enable",
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| "chip enable port polarity": "active high",
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| "output port name": "data_out",
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| "output port polarity": "active high",
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| "input port name": "data_in",
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| "input port polarity": "active high",
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| "mask port name": "mask",
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| "mask port polarity": "active high",
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| "mask granularity": 8
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| }
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| ]
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| }
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|""".stripMargin
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}
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}
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// Tests for filler macros.
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class FillerMacroOutput extends AnyFlatSpec with Matchers {
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"Valid lvt macro" should "be generated" in {
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val expected = """
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| {
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| "type": "filler cell",
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| "name": "MY_FILLER_CELL",
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| "vt": "lvt"
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| }
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|""".stripMargin
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FillerMacro("MY_FILLER_CELL", "lvt").toJSON shouldBe Json.parse(expected)
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}
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"Valid metal macro" should "be generated" in {
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val expected = """
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| {
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| "type": "metal filler cell",
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| "name": "METAL_FILLER_CELL",
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| "vt": "lvt"
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| }
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|""".stripMargin
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MetalFillerMacro("METAL_FILLER_CELL", "lvt").toJSON shouldBe Json.parse(expected)
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}
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"Valid hvt macro" should "be generated" in {
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val expected = """
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| {
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| "type": "filler cell",
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| "name": "HVT_CELL_PROP",
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| "vt": "hvt"
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| }
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|""".stripMargin
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FillerMacro("HVT_CELL_PROP", "hvt").toJSON shouldBe Json.parse(expected)
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}
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}
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class SRAMPortOutput extends AnyFlatSpec with Matchers {
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"Extra port" should "be generated" in {
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val m = MacroExtraPort(
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name = "TIE_HIGH",
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width = 8,
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portType = Constant,
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value = ((1 << 8) - 1)
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)
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val expected = """
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| {
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| "type": "constant",
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| "name": "TIE_HIGH",
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| "width": 8,
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| "value": 255
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| }
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|""".stripMargin
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m.toJSON shouldBe Json.parse(expected)
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}
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"Minimal write port" should "be generated" in {
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val m = MacroPort(
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address = PolarizedPort(name = "addr", polarity = ActiveHigh),
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clock = Some(PolarizedPort(name = "clk", polarity = PositiveEdge)),
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writeEnable = Some(PolarizedPort(name = "write_enable", polarity = ActiveHigh)),
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input = Some(PolarizedPort(name = "data_in", polarity = ActiveHigh)),
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width = Some(32),
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depth = Some(1024) // These numbers don't matter.
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)
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val expected = """
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| {
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| "address port name": "addr",
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| "address port polarity": "active high",
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| "clock port name": "clk",
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| "clock port polarity": "positive edge",
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| "write enable port name": "write_enable",
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| "write enable port polarity": "active high",
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| "input port name": "data_in",
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| "input port polarity": "active high"
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| }
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|""".stripMargin
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m.toJSON shouldBe Json.parse(expected)
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}
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"Minimal read port" should "be generated" in {
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val m = MacroPort(
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address = PolarizedPort(name = "addr", polarity = ActiveHigh),
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clock = Some(PolarizedPort(name = "clk", polarity = PositiveEdge)),
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output = Some(PolarizedPort(name = "data_out", polarity = ActiveHigh)),
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width = Some(32),
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depth = Some(1024) // These numbers don't matter.
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)
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val expected = """
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| {
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| "address port name": "addr",
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| "address port polarity": "active high",
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| "clock port name": "clk",
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| "clock port polarity": "positive edge",
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| "output port name": "data_out",
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| "output port polarity": "active high"
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| }
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|""".stripMargin
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m.toJSON shouldBe Json.parse(expected)
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}
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"Masked read port" should "be generated" in {
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val m = MacroPort(
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address = PolarizedPort(name = "addr", polarity = ActiveHigh),
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clock = Some(PolarizedPort(name = "clk", polarity = PositiveEdge)),
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output = Some(PolarizedPort(name = "data_out", polarity = ActiveHigh)),
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maskPort = Some(PolarizedPort(name = "mask", polarity = ActiveHigh)),
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maskGran = Some(8),
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width = Some(32),
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depth = Some(1024) // These numbers don't matter.
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)
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val expected = """
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| {
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| "address port name": "addr",
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| "address port polarity": "active high",
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| "clock port name": "clk",
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| "clock port polarity": "positive edge",
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| "output port name": "data_out",
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| "output port polarity": "active high",
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| "mask port name": "mask",
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| "mask port polarity": "active high",
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| "mask granularity": 8
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| }
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|""".stripMargin
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m.toJSON shouldBe Json.parse(expected)
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}
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"Everything port" should "be generated" in {
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val m = MacroPort(
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address = PolarizedPort(name = "addr", polarity = ActiveHigh),
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clock = Some(PolarizedPort(name = "clk", polarity = PositiveEdge)),
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writeEnable = Some(PolarizedPort(name = "write_enable", polarity = ActiveHigh)),
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readEnable = Some(PolarizedPort(name = "read_enable", polarity = ActiveHigh)),
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chipEnable = Some(PolarizedPort(name = "chip_enable", polarity = ActiveHigh)),
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output = Some(PolarizedPort(name = "data_out", polarity = ActiveHigh)),
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input = Some(PolarizedPort(name = "data_in", polarity = ActiveHigh)),
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maskPort = Some(PolarizedPort(name = "mask", polarity = ActiveHigh)),
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maskGran = Some(8),
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width = Some(32),
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depth = Some(1024) // These numbers don't matter.
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)
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val expected = """
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| {
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| "address port name": "addr",
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| "address port polarity": "active high",
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| "clock port name": "clk",
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| "clock port polarity": "positive edge",
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| "write enable port name": "write_enable",
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| "write enable port polarity": "active high",
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| "read enable port name": "read_enable",
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| "read enable port polarity": "active high",
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| "chip enable port name": "chip_enable",
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| "chip enable port polarity": "active high",
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| "output port name": "data_out",
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| "output port polarity": "active high",
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| "input port name": "data_in",
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| "input port polarity": "active high",
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| "mask port name": "mask",
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| "mask port polarity": "active high",
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| "mask granularity": 8
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| }
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|""".stripMargin
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m.toJSON shouldBe Json.parse(expected)
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}
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}
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class SRAMMacroOutput extends AnyFlatSpec with Matchers with HasAwesomeMemData {
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"SRAM macro" should "be generated" in {
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val m = getAwesomeMem
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val expected = getAwesomeMemJSON
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m.toJSON shouldBe Json.parse(expected)
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}
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}
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class InputOutput extends AnyFlatSpec with Matchers with HasAwesomeMemData {
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"Read-write string" should "preserve data" in {
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val mdf = List(
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FillerMacro("MY_FILLER_CELL", "lvt"),
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MetalFillerMacro("METAL_GEAR_FILLER", "hvt"),
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getAwesomeMem
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)
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Utils.readMDFFromString(Utils.writeMDFToString(mdf)) shouldBe Some(mdf)
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}
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val testDir: String = "test_run_dir"
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new File(testDir).mkdirs // Make sure the testDir exists
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"Read-write file" should "preserve data" in {
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val mdf = List(
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FillerMacro("MY_FILLER_CELL", "lvt"),
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MetalFillerMacro("METAL_GEAR_FILLER", "hvt"),
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getAwesomeMem
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)
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val filename = testDir + "/" + "mdf_read_write_test.json"
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Utils.writeMDFToPath(Some(filename), mdf) shouldBe true
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Utils.readMDFFromPath(Some(filename)) shouldBe Some(mdf)
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}
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}
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