From afff9c4243371af924904b02a0b8ead4b19da956 Mon Sep 17 00:00:00 2001 From: joonho hwangbo Date: Wed, 15 May 2024 23:56:06 -0700 Subject: [PATCH 01/51] Misc configs | rocketchip bump (#1877) * Misc configs | rocketchip bump * Add NoTraceIOBridge * Nit * Remove useless configs * FireSim NoC config --- .../src/main/scala/config/NoCConfigs.scala | 23 +++++++++++++++++++ .../src/main/scala/config/RocketConfigs.scala | 4 ++++ .../src/main/scala/TargetConfigs.scala | 8 ++++++- generators/rocket-chip | 2 +- 4 files changed, 35 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala index a5acc1e0..ac24d85c 100644 --- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala @@ -267,3 +267,26 @@ class SbusMeshNoCConfig extends Config( new chipyard.config.AbstractConfig ) +class QuadRocketSbusRingNoCConfig extends Config( + new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams( + constellation.protocol.DiplomaticNetworkNodeMapping( + inNodeMapping = ListMap( + "Core 0 " -> 0, + "Core 1 " -> 1, + "Core 2 " -> 2, + "Core 3 " -> 3, + "serial_tl" -> 4), + outNodeMapping = ListMap( + "system[0]" -> 5, + "system[1]" -> 6, + "system[2]" -> 7, + "system[3]" -> 8, + "pbus" -> 4)), // TSI is on the pbus, so serial-tl and pbus should be on the same node + nocParams = NoCParams( + topology = UnidirectionalTorus1D(9), + channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }), + routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 5, 2)) + )) ++ + new freechips.rocketchip.subsystem.WithNBigCores(4) ++ + new freechips.rocketchip.subsystem.WithNBanks(4) ++ + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index d3f21584..680129a3 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -12,6 +12,10 @@ class RocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) +class DualRocketConfig extends Config( + new freechips.rocketchip.subsystem.WithNBigCores(2) ++ + new chipyard.config.AbstractConfig) + class TinyRocketConfig extends Config( new chipyard.harness.WithDontTouchChipTopPorts(false) ++ // TODO FIX: Don't dontTouch the ports new testchipip.soc.WithNoScratchpads ++ // All memory is the Rocket TCMs diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 8533d80b..42f0b1d8 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -371,10 +371,16 @@ class FireSimLargeBoomCospikeConfig extends Config( new WithFireSimConfigTweaks++ new chipyard.LargeBoomV3Config) +class FireSimQuadRocketSbusRingNoCConfig extends Config( + new chipyard.config.WithNoTraceIO ++ + new WithDefaultFireSimBridges ++ + new WithFireSimConfigTweaks++ + new chipyard.QuadRocketSbusRingNoCConfig) + class FireSimLargeBoomSV39CospikeConfig extends Config( new firesim.firesim.WithCospikeBridge ++ new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ new WithFireSimConfigTweaks++ new chipyard.config.WithSV39 ++ - new chipyard.LargeBoomV3Config) + new chipyard.LargeBoomV3Config) \ No newline at end of file diff --git a/generators/rocket-chip b/generators/rocket-chip index c10ce93f..e79ecc10 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit c10ce93fd1a4187599ea926603e8ce10d04f77d7 +Subproject commit e79ecc100b5d20cc32ce426d0d7440bbfaf29e61 From c60d0475b64f7fa6822dd5b476572c4afa5ce7f6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 May 2024 09:46:06 -0700 Subject: [PATCH 02/51] remove redundant CLASSPATH_TARGETS (this is always the same as CLASSPATH) --- common.mk | 10 +++++----- variables.mk | 3 --- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/common.mk b/common.mk index a0f3e6ac..8aa41ca7 100644 --- a/common.mk +++ b/common.mk @@ -119,13 +119,13 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip ######################################################################################### # compile scala jars ######################################################################################### -$(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES) +$(CHIPYARD_CLASSPATH) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES) $(CHECK_SUBMODULES_COMMAND) mkdir -p $(dir $@) $(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH)) # order only dependency between sbt runs needed to avoid concurrent sbt runs -$(TAPEOUT_CLASSPATH_TARGETS) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH_TARGETS) +$(TAPEOUT_CLASSPATH) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH) mkdir -p $(dir $@) $(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH)) @@ -133,7 +133,7 @@ $(TAPEOUT_CLASSPATH_TARGETS) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) # verilog generation pipeline ######################################################################################### # AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile -$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(CHIPYARD_CLASSPATH_TARGETS) $(EXTRA_GENERATOR_REQS) +$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(CHIPYARD_CLASSPATH) $(EXTRA_GENERATOR_REQS) mkdir -p $(build_dir) (set -o pipefail && $(call run_jar_scala_main,$(CHIPYARD_CLASSPATH),$(GENERATOR_PACKAGE).Generator,\ --target-dir $(build_dir) \ @@ -242,12 +242,12 @@ $(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JS # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs TOP_MACROCOMPILER_MODE ?= --mode synflops -$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(TOP_SMEMS_CONF) +$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH) $(TOP_SMEMS_CONF) $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE)) touch $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) MODEL_MACROCOMPILER_MODE = --mode synflops -$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_SMEMS_CONF) +$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH) $(MODEL_SMEMS_CONF) $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE)) touch $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) diff --git a/variables.mk b/variables.mk index 58cc85c4..e58e7f73 100644 --- a/variables.mk +++ b/variables.mk @@ -162,9 +162,6 @@ endif CLASSPATH_CACHE ?= $(base_dir)/.classpath_cache CHIPYARD_CLASSPATH ?= $(CLASSPATH_CACHE)/chipyard.jar TAPEOUT_CLASSPATH ?= $(CLASSPATH_CACHE)/tapeout.jar -# if *_CLASSPATH is a true java classpath, it can be colon-delimited list of paths (on *nix) -CHIPYARD_CLASSPATH_TARGETS ?= $(subst :, ,$(CHIPYARD_CLASSPATH)) -TAPEOUT_CLASSPATH_TARGETS ?= $(subst :, ,$(TAPEOUT_CLASSPATH)) # chisel generated outputs FIRRTL_FILE ?= $(build_dir)/$(long_name).fir From 9737d62635bd24208d3049f56b8a3b5946b76531 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 May 2024 09:50:36 -0700 Subject: [PATCH 03/51] Add comments on what CHIPYARD_CLASSPATH and TAPEOUT_CLASSPATH contain --- variables.mk | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/variables.mk b/variables.mk index e58e7f73..9c7d159a 100644 --- a/variables.mk +++ b/variables.mk @@ -160,7 +160,9 @@ endif # classpaths CLASSPATH_CACHE ?= $(base_dir)/.classpath_cache -CHIPYARD_CLASSPATH ?= $(CLASSPATH_CACHE)/chipyard.jar +# The chipyard classpath must contain the Generator main +CHIPYARD_CLASSPATH ?= $(CLASSPATH_CACHE)/$(SBT_PROJECT).jar +# The tapeout classpath must contain MacroCompiler TAPEOUT_CLASSPATH ?= $(CLASSPATH_CACHE)/tapeout.jar # chisel generated outputs From 0c3ede15af603c2e6a6e5e3a777a206a6cc04546 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 May 2024 09:51:40 -0700 Subject: [PATCH 04/51] Rename CHIPYARD_CLASSPATH to GENERATOR_CLASSPATH This name better reflects that this classpath must contain a Generator main, but does not have to necessarily be the chipyard project in build.sbt --- common.mk | 10 +++++----- variables.mk | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/common.mk b/common.mk index 8aa41ca7..04d1374e 100644 --- a/common.mk +++ b/common.mk @@ -119,13 +119,13 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip ######################################################################################### # compile scala jars ######################################################################################### -$(CHIPYARD_CLASSPATH) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES) +$(GENERATOR_CLASSPATH) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES) $(CHECK_SUBMODULES_COMMAND) mkdir -p $(dir $@) - $(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH)) + $(call run_sbt_assembly,$(SBT_PROJECT),$(GENERATOR_CLASSPATH)) # order only dependency between sbt runs needed to avoid concurrent sbt runs -$(TAPEOUT_CLASSPATH) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH) +$(TAPEOUT_CLASSPATH) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(GENERATOR_CLASSPATH) mkdir -p $(dir $@) $(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH)) @@ -133,9 +133,9 @@ $(TAPEOUT_CLASSPATH) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEO # verilog generation pipeline ######################################################################################### # AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile -$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(CHIPYARD_CLASSPATH) $(EXTRA_GENERATOR_REQS) +$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(GENERATOR_CLASSPATH) $(EXTRA_GENERATOR_REQS) mkdir -p $(build_dir) - (set -o pipefail && $(call run_jar_scala_main,$(CHIPYARD_CLASSPATH),$(GENERATOR_PACKAGE).Generator,\ + (set -o pipefail && $(call run_jar_scala_main,$(GENERATOR_CLASSPATH),$(GENERATOR_PACKAGE).Generator,\ --target-dir $(build_dir) \ --name $(long_name) \ --top-module $(MODEL_PACKAGE).$(MODEL) \ diff --git a/variables.mk b/variables.mk index 9c7d159a..8fadc084 100644 --- a/variables.mk +++ b/variables.mk @@ -160,8 +160,8 @@ endif # classpaths CLASSPATH_CACHE ?= $(base_dir)/.classpath_cache -# The chipyard classpath must contain the Generator main -CHIPYARD_CLASSPATH ?= $(CLASSPATH_CACHE)/$(SBT_PROJECT).jar +# The generator classpath must contain the Generator main +GENERATOR_CLASSPATH ?= $(CLASSPATH_CACHE)/$(SBT_PROJECT).jar # The tapeout classpath must contain MacroCompiler TAPEOUT_CLASSPATH ?= $(CLASSPATH_CACHE)/tapeout.jar From 3cf3d815dc6a88113637be022e3aa0fda3a14763 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 May 2024 09:53:48 -0700 Subject: [PATCH 05/51] Rename fpga_platforms to chipyard_fpga --- build.sbt | 2 +- docs/Prototyping/General.rst | 2 +- fpga/Makefile | 10 +++++----- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/build.sbt b/build.sbt index dd245a6f..fb38ee68 100644 --- a/build.sbt +++ b/build.sbt @@ -324,6 +324,6 @@ lazy val fpga_shells = (project in file("./fpga/fpga-shells")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val fpga_platforms = (project in file("./fpga")) +lazy val chipyard_fpga = (project in file("./fpga")) .dependsOn(chipyard, fpga_shells) .settings(commonSettings) diff --git a/docs/Prototyping/General.rst b/docs/Prototyping/General.rst index 051cbcf8..17ef4173 100644 --- a/docs/Prototyping/General.rst +++ b/docs/Prototyping/General.rst @@ -30,7 +30,7 @@ For example: # converts to - make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 FPGA_BRAND=... bitstream + make SBT_PROJECT=chipyard_fpga MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 FPGA_BRAND=... bitstream Some ``SUB_PROJECT`` defaults are already defined for use, including ``vcu118`` and ``arty``. These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more for the Chipyard make system. diff --git a/fpga/Makefile b/fpga/Makefile index ebf55a97..22f7ce18 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -17,7 +17,7 @@ sim_name := none SUB_PROJECT ?= vcu118 ifeq ($(SUB_PROJECT),vc707) - SBT_PROJECT ?= fpga_platforms + SBT_PROJECT ?= chipyard_fpga MODEL ?= VC707FPGATestHarness VLOG_MODEL ?= VC707FPGATestHarness MODEL_PACKAGE ?= chipyard.fpga.vc707 @@ -31,7 +31,7 @@ ifeq ($(SUB_PROJECT),vc707) endif ifeq ($(SUB_PROJECT),vcu118) - SBT_PROJECT ?= fpga_platforms + SBT_PROJECT ?= chipyard_fpga MODEL ?= VCU118FPGATestHarness VLOG_MODEL ?= VCU118FPGATestHarness MODEL_PACKAGE ?= chipyard.fpga.vcu118 @@ -45,7 +45,7 @@ ifeq ($(SUB_PROJECT),vcu118) endif ifeq ($(SUB_PROJECT),nexysvideo) - SBT_PROJECT ?= fpga_platforms + SBT_PROJECT ?= chipyard_fpga MODEL ?= NexysVideoHarness VLOG_MODEL ?= NexysVideoHarness MODEL_PACKAGE ?= chipyard.fpga.nexysvideo @@ -60,7 +60,7 @@ endif ifeq ($(SUB_PROJECT),arty35t) # TODO: Fix with Arty - SBT_PROJECT ?= fpga_platforms + SBT_PROJECT ?= chipyard_fpga MODEL ?= Arty35THarness VLOG_MODEL ?= Arty35THarness MODEL_PACKAGE ?= chipyard.fpga.arty @@ -74,7 +74,7 @@ ifeq ($(SUB_PROJECT),arty35t) endif ifeq ($(SUB_PROJECT),arty100t) # TODO: Fix with Arty - SBT_PROJECT ?= fpga_platforms + SBT_PROJECT ?= chipyard_fpga MODEL ?= Arty100THarness VLOG_MODEL ?= Arty100THarness MODEL_PACKAGE ?= chipyard.fpga.arty100t From 2f2cde8748d1dbc38dcfc5c76dd93435571a3f06 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 17 May 2024 12:13:44 -0700 Subject: [PATCH 06/51] Bump rocket-chip --- generators/rocket-chip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/rocket-chip b/generators/rocket-chip index e79ecc10..a2356842 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit e79ecc100b5d20cc32ce426d0d7440bbfaf29e61 +Subproject commit a2356842423c884863140745f686ec81d3544d07 From 5c57d8733bbd8eb437c3d41d876294e2db7cce35 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 17 May 2024 12:47:17 -0700 Subject: [PATCH 07/51] Bump shuttle/boom --- generators/boom | 2 +- generators/shuttle | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/boom b/generators/boom index 506c11c9..41c8fc9b 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 506c11c99ca9f6015d14fdc02c45c1e22983d06f +Subproject commit 41c8fc9bdfe68d0e30295cbaf764f2e69c36dbb8 diff --git a/generators/shuttle b/generators/shuttle index b75fada2..4792a1ab 160000 --- a/generators/shuttle +++ b/generators/shuttle @@ -1 +1 @@ -Subproject commit b75fada257c576de5c9968dbbf5a09302b53b1de +Subproject commit 4792a1aba4e9f2d70e6f84587913f78c9e4c0340 From 3a6677bc3012f47e94b8914ebab6e789c9e949e3 Mon Sep 17 00:00:00 2001 From: Nayiri <38256927+nayiri-k@users.noreply.github.com> Date: Sun, 19 May 2024 17:54:47 -0700 Subject: [PATCH 08/51] Fix clock name and macro paths for Sky130 VLSI flow (#1882) --- vlsi/example-asap7.yml | 2 +- vlsi/example-design.yml | 2 +- vlsi/example-designs/sky130-commercial.yml | 2 +- .../sky130-openroad-rockettile.yml | 5 ++-- vlsi/example-designs/sky130-openroad.yml | 23 ++++++------------- vlsi/example-designs/sky130-rocket.yml | 2 +- vlsi/example-sky130.yml | 12 +++++----- 7 files changed, 20 insertions(+), 28 deletions(-) diff --git a/vlsi/example-asap7.yml b/vlsi/example-asap7.yml index 6fc819aa..ab0d6c8e 100644 --- a/vlsi/example-asap7.yml +++ b/vlsi/example-asap7.yml @@ -17,7 +17,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_uncore_clock", period: "1ns", uncertainty: "0.1ns"} + {name: "clock_uncore", period: "1ns", uncertainty: "0.1ns"} ] # Generate Make include to aid in flow diff --git a/vlsi/example-design.yml b/vlsi/example-design.yml index 3f46a443..80f338a9 100644 --- a/vlsi/example-design.yml +++ b/vlsi/example-design.yml @@ -10,7 +10,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_uncore_clock", period: "2ns", uncertainty: "0.1ns"} + {name: "clock_uncore", period: "2ns", uncertainty: "0.1ns"} ] # Specify pin properties diff --git a/vlsi/example-designs/sky130-commercial.yml b/vlsi/example-designs/sky130-commercial.yml index fb1f8407..1ec4a08f 100644 --- a/vlsi/example-designs/sky130-commercial.yml +++ b/vlsi/example-designs/sky130-commercial.yml @@ -2,7 +2,7 @@ # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_uncore_clock", period: "30ns", uncertainty: "2ns"} + {name: "clock_uncore", period: "30ns", uncertainty: "2ns"} ] # Placement Constraints diff --git a/vlsi/example-designs/sky130-openroad-rockettile.yml b/vlsi/example-designs/sky130-openroad-rockettile.yml index 4a6b664c..cfc4c5bb 100644 --- a/vlsi/example-designs/sky130-openroad-rockettile.yml +++ b/vlsi/example-designs/sky130-openroad-rockettile.yml @@ -1,7 +1,7 @@ # Override configurations in ../example-sky130.yml and example-designs # Specify clock signals -# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock" +# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore" vlsi.inputs.clocks: [ {name: "clock", period: "30ns", uncertainty: "3ns"} ] @@ -22,7 +22,7 @@ vlsi.inputs.placement_constraints: bottom: 10 # Place SRAM memory instances - # data cache + # data cache - path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" type: hardmacro x: 50 @@ -47,3 +47,4 @@ vlsi.inputs.placement_constraints: x: 50 y: 2100 orientation: r90 + diff --git a/vlsi/example-designs/sky130-openroad.yml b/vlsi/example-designs/sky130-openroad.yml index 3b95d982..a686fbba 100644 --- a/vlsi/example-designs/sky130-openroad.yml +++ b/vlsi/example-designs/sky130-openroad.yml @@ -3,7 +3,7 @@ # Specify clock signals # Relax the clock period for OpenROAD to meet timing vlsi.inputs.clocks: [ - {name: "clock_uncore_clock", period: "50ns", uncertainty: "2ns"} + {name: "clock_uncore", period: "50ns", uncertainty: "2ns"} ] # Flow parameters that yield a routable design with reasonable timing @@ -54,36 +54,27 @@ vlsi.inputs.placement_constraints: bottom: 10 # Place SRAM memory instances - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" + # data cache + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" type: hardmacro x: 50 y: 50 orientation: r90 - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" type: hardmacro x: 50 - y: 450 - orientation: r90 - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0" - type: hardmacro - x: 50 - y: 850 - orientation: r90 - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0" - type: hardmacro - x: 50 - y: 1250 + y: 800 orientation: r90 # tag array - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" type: hardmacro x: 50 y: 1600 orientation: r90 # instruction cache - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 50 y: 2100 diff --git a/vlsi/example-designs/sky130-rocket.yml b/vlsi/example-designs/sky130-rocket.yml index 2e7c7a5b..7e95e331 100644 --- a/vlsi/example-designs/sky130-rocket.yml +++ b/vlsi/example-designs/sky130-rocket.yml @@ -1,7 +1,7 @@ # Override configurations in ../example-sky130.yml and example-designs # Specify clock signals -# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock" +# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore" vlsi.inputs.clocks: [ {name: "clock", period: "5ns", uncertainty: "1ns"} ] diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml index 1e3faf1c..3f45bd3d 100644 --- a/vlsi/example-sky130.yml +++ b/vlsi/example-sky130.yml @@ -20,7 +20,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_uncore_clock", period: "20ns", uncertainty: "1ns"} + {name: "clock_uncore", period: "20ns", uncertainty: "1ns"} ] # Generate Make include to aid in flow @@ -42,27 +42,27 @@ vlsi.inputs.placement_constraints: bottom: 10 # Place SRAM memory instances - # data cache - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" + # data cache + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" type: hardmacro x: 50 y: 50 orientation: r90 - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" type: hardmacro x: 50 y: 800 orientation: r90 # tag array - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" type: hardmacro x: 50 y: 1600 orientation: r90 # instruction cache - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 50 y: 2100 From 16bc0531e9ca3af5001b1e2fc8fa857aeb9aeac1 Mon Sep 17 00:00:00 2001 From: bartender Date: Mon, 20 May 2024 01:29:10 +0000 Subject: [PATCH 09/51] [cd] Bump CIRCT from firtool-1.66.0 to firtool-1.75.0 This is an automated commit generated by the `circt/update-circt` GitHub Action. (cherry picked from commit 0a4a055f375bec7620ab38e2704261d73385cfd7) --- conda-reqs/circt.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/conda-reqs/circt.json b/conda-reqs/circt.json index 1eb54a43..020fe373 100644 --- a/conda-reqs/circt.json +++ b/conda-reqs/circt.json @@ -1,3 +1,3 @@ { - "version": "firtool-1.66.0" + "version": "firtool-1.75.0" } From 3c31faef7b96eedd502a28b16891c58ec709d114 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 23 May 2024 12:50:20 -0700 Subject: [PATCH 10/51] Add GCD IOBinders examples --- .../chipyard/src/main/scala/config/AbstractConfig.scala | 1 + .../chipyard/src/main/scala/iobinders/IOBinders.scala | 9 +++++++++ generators/chipyard/src/main/scala/iobinders/Ports.scala | 2 ++ 3 files changed, 12 insertions(+) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 77a998e6..11d70982 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -59,6 +59,7 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithNICIOPunchthrough ++ new chipyard.iobinders.WithTraceIOPunchthrough ++ new chipyard.iobinders.WithUARTTSIPunchthrough ++ + new chipyard.iobinders.WithGCDBusyPunchthrough ++ new chipyard.iobinders.WithNMITiedOff ++ diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index e00f43a4..61f34744 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -39,6 +39,7 @@ import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig} import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO} import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule} +import chipyard.example.{CanHavePeripheryGCD} import scala.reflect.{ClassTag} @@ -540,3 +541,11 @@ class WithNMITiedOff extends ComposeIOBinder({ (Nil, Nil) } }) + +class WithGCDBusyPunchthrough extends OverrideIOBinder({ + (system: CanHavePeripheryGCD) => system.gcd_busy.map { busy => + val io_gcd_busy = IO(Output(Bool())) + io_gcd_busy := busy + (Seq(GCDBusyPort(() => io_gcd_busy)), Nil) + }.getOrElse((Nil, Nil)) +}) diff --git a/generators/chipyard/src/main/scala/iobinders/Ports.scala b/generators/chipyard/src/main/scala/iobinders/Ports.scala index a9ea0a2d..dfe9c58f 100644 --- a/generators/chipyard/src/main/scala/iobinders/Ports.scala +++ b/generators/chipyard/src/main/scala/iobinders/Ports.scala @@ -109,3 +109,5 @@ case class JTAGResetPort (val getIO: () => Reset) case class TLMemPort (val getIO: () => HeterogeneousBag[TLBundle]) extends Port[HeterogeneousBag[TLBundle]] +case class GCDBusyPort (val getIO: () => Bool) + extends Port[Bool] From 9a5673ddef7e5dd925a3a0d352553b85f1e973c9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 5 May 2023 11:26:27 -0700 Subject: [PATCH 11/51] Add singleclock broadcast clockbinder --- .../main/scala/clocking/ClockBinders.scala | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index d075fcbb..3582ba08 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -102,6 +102,42 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({ } }) +// Broadcasts a single clock IO to all clock domains +class WithSingleClockBroadcastClockGenerator extends OverrideLazyIOBinder({ + (system: HasChipyardPRCI) => { + implicit val p = GetSystemParameters(system) + val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) + system.connectImplicitClockSinkNode(implicitClockSinkNode) + InModuleBody { + val implicit_clock = implicitClockSinkNode.in.head._1.clock + val implicit_reset = implicitClockSinkNode.in.head._1.reset + system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => { + l.clock := implicit_clock + l.reset := implicit_reset + }} + } + + val clockGroupsAggregateNode = ClockGroupAggregateNode("single_clock") + val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) + system.allClockGroupsNode :*= clockGroupsAggregateNode := clockGroupsSourceNode + + InModuleBody { + val clock_wire = Wire(Input(new ClockWithFreq(100))) + val reset_wire = Wire(Input(AsyncReset())) + val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey)) + val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey)) + + clockGroupsSourceNode.out.foreach { case (bundle, edge) => + bundle.member.data.foreach { b => + b.clock := clock_io.clock + b.reset := reset_io + } + } + (Seq(clock_io, reset_io), clockIOCell ++ resetIOCell) + } + } +}) + class WithClockTapIOCells extends OverrideIOBinder({ (system: CanHaveClockTap) => { system.clockTapIO.map { tap => From 17f784bfd331cc7335dae49e5b26054342a1c252 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 28 May 2024 12:26:18 -0700 Subject: [PATCH 12/51] Add example clocking configs and SingleClockBroadcast option --- .../main/scala/clocking/ClockBinders.scala | 26 +++++--------- .../main/scala/config/ClockingConfigs.scala | 34 +++++++++++++++++++ 2 files changed, 42 insertions(+), 18 deletions(-) create mode 100644 generators/chipyard/src/main/scala/config/ClockingConfigs.scala diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index 3582ba08..bcf2fb49 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -72,7 +72,7 @@ class WithPLLSelectorDividerClockGenerator(enable: Boolean = true) extends Overr } } }) - + // This passes all clocks through to the TestHarness class WithPassthroughClockGenerator extends OverrideLazyIOBinder({ (system: HasChipyardPRCI) => { @@ -102,38 +102,28 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({ } }) -// Broadcasts a single clock IO to all clock domains -class WithSingleClockBroadcastClockGenerator extends OverrideLazyIOBinder({ +// Broadcasts a single clock IO to all clock domains. Ignores all requested frequencies +class WithSingleClockBroadcastClockGenerator(freqMHz: Int = 100) extends OverrideLazyIOBinder({ (system: HasChipyardPRCI) => { implicit val p = GetSystemParameters(system) - val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) - system.connectImplicitClockSinkNode(implicitClockSinkNode) - InModuleBody { - val implicit_clock = implicitClockSinkNode.in.head._1.clock - val implicit_reset = implicitClockSinkNode.in.head._1.reset - system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => { - l.clock := implicit_clock - l.reset := implicit_reset - }} - } - val clockGroupsAggregateNode = ClockGroupAggregateNode("single_clock") + val clockGroupsAggregator = LazyModule(new ClockGroupAggregator("single_clock")) val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) - system.allClockGroupsNode :*= clockGroupsAggregateNode := clockGroupsSourceNode + system.chiptopClockGroupsNode :*= clockGroupsAggregator.node := clockGroupsSourceNode InModuleBody { - val clock_wire = Wire(Input(new ClockWithFreq(100))) + val clock_wire = Wire(Input(Clock())) val reset_wire = Wire(Input(AsyncReset())) val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey)) val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey)) clockGroupsSourceNode.out.foreach { case (bundle, edge) => bundle.member.data.foreach { b => - b.clock := clock_io.clock + b.clock := clock_io b.reset := reset_io } } - (Seq(clock_io, reset_io), clockIOCell ++ resetIOCell) + (Seq(ClockPort(() => clock_io, freqMHz), ResetPort(() => reset_io)), clockIOCell ++ resetIOCell) } } }) diff --git a/generators/chipyard/src/main/scala/config/ClockingConfigs.scala b/generators/chipyard/src/main/scala/config/ClockingConfigs.scala new file mode 100644 index 00000000..0d3197ea --- /dev/null +++ b/generators/chipyard/src/main/scala/config/ClockingConfigs.scala @@ -0,0 +1,34 @@ +package chipyard + +import org.chipsalliance.cde.config.{Config} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.subsystem.{MBUS, SBUS} +import testchipip.soc.{OBUS} + +//================================================== +// This file contains examples of the different ways +// clocks can be generated for chiypard designs +//================================================== + +// The default constructs IOs for all requested clocks in the chiptopClockGroupsNode +// Note: This is what designs inheriting from AbstractConfig do by default +class DefaultClockingRocketConfig extends Config( + new chipyard.clocking.WithPassthroughClockGenerator ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + +// This is a more physically realistic approach, normally we can't punch out a separate +// pin for each clock domain. The standard "test chip" approach is to punch a few slow clock +// inputs, integrate a PLL, and generate an array of selectors/dividers to configure the +// clocks for each domain. See the source for WithPLLSelectorDividerClockGenerator for more info +class ChipLikeClockingRocketConfig extends Config( + new chipyard.clocking.WithPLLSelectorDividerClockGenerator ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + +// This merges all the clock domains in chiptopClockGroupsNode into one, then generates a single +// clock input pin. +class SingleClockBroadcastRocketConfig extends Config( + new chipyard.clocking.WithSingleClockBroadcastClockGenerator ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) From 385c055ef78df44a61812149942af5f2d233704d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 2 Feb 2024 16:20:10 -0800 Subject: [PATCH 13/51] Add rerocc submodule --- .gitmodules | 4 +++- generators/rerocc | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) create mode 160000 generators/rerocc diff --git a/.gitmodules b/.gitmodules index cc56bc35..c24ded76 100644 --- a/.gitmodules +++ b/.gitmodules @@ -142,4 +142,6 @@ [submodule "tools/midas-targetutils"] path = tools/midas-targetutils url = https://github.com/firesim/midas-targetutils.git - +[submodule "generators/rerocc"] + path = generators/rerocc + url = https://github.com/ucb-bar/rerocc.git diff --git a/generators/rerocc b/generators/rerocc new file mode 160000 index 00000000..78a29b0f --- /dev/null +++ b/generators/rerocc @@ -0,0 +1 @@ +Subproject commit 78a29b0f885deef1a99fb071dd6feeb7b65702b9 From e8eeaad36d71666b2a95365319956f6079134433 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 2 Feb 2024 16:20:46 -0800 Subject: [PATCH 14/51] Add rerocc to check-commit CI --- .github/scripts/check-commit.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index 570a6ee5..1b859414 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -45,7 +45,8 @@ search () { done } -submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy") + +submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc") dir="generators" branches=("master" "main" "dev") search From fdb47267704d4022ef2a14763ccd2cbf6d71cdf8 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 2 Feb 2024 16:21:34 -0800 Subject: [PATCH 15/51] Add rerocc to build.sbt --- build.sbt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index f240389f..4bb7c4c6 100644 --- a/build.sbt +++ b/build.sbt @@ -173,7 +173,7 @@ lazy val chipyard = (project in file("generators/chipyard")) .dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache, dsptools, rocket_dsp_utils, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, - constellation, mempress, barf, shuttle, caliptra_aes) + constellation, mempress, barf, shuttle, caliptra_aes, rerocc) .settings(libraryDependencies ++= rocketLibDeps.value) .settings( libraryDependencies ++= Seq( @@ -253,6 +253,11 @@ lazy val caliptra_aes = (project in file("generators/caliptra-aes-acc")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) +lazy val rerocc = (project in file("generators/rerocc")) + .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(commonSettings) + lazy val rocc_acc_utils = (project in file("generators/rocc-acc-utils")) .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) From 13dda467644e6baeb3d20f98005d93be5b7b62fb Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 5 Feb 2024 11:11:59 -0800 Subject: [PATCH 16/51] Integrate rerocc --- build.sbt | 2 +- .../chipyard/src/main/scala/DigitalTop.scala | 1 + .../scala/config/RoCCAcceleratorConfigs.scala | 19 +++++++++++++++++++ .../config/fragments/RoCCFragments.scala | 14 ++++++++++++++ generators/rerocc | 2 +- 5 files changed, 36 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index 4bb7c4c6..36bf7742 100644 --- a/build.sbt +++ b/build.sbt @@ -254,7 +254,7 @@ lazy val caliptra_aes = (project in file("generators/caliptra-aes-acc")) .settings(commonSettings) lazy val rerocc = (project in file("generators/rerocc")) - .dependsOn(rocketchip) + .dependsOn(rocketchip, constellation, boom) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index e0f69392..c4fa17aa 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -39,6 +39,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with chipyard.clocking.CanHaveClockTap // Enables optionally adding a clock tap output port with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect + with rerocc.CanHaveReRoCCTiles // Support tiles that instantiate rerocc-attached accelerators { override lazy val module = new DigitalTopModule(this) } diff --git a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala index 184afaa7..91ee7c15 100644 --- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala @@ -48,3 +48,22 @@ class AES256ECBRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.WithSystemBusWidth(256) ++ new chipyard.config.AbstractConfig) + +class ReRoCCTestConfig extends Config( + new rerocc.WithReRoCC ++ + new chipyard.config.WithCharacterCountRoCC ++ // rerocc tile4 is charcnt + new chipyard.config.WithAccumulatorRoCC ++ // rerocc tile3 is accum + new chipyard.config.WithAccumulatorRoCC ++ // rerocc tile2 is accum + new chipyard.config.WithAccumulatorRoCC ++ // rerocc tile1 is accum + new chipyard.config.WithAccumulatorRoCC ++ // rerocc tile0 is accum + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) + +class ReRoCCManyGemminiConfig extends Config( + new rerocc.WithReRoCC ++ + new gemmini.LeanGemminiConfig ++ // rerocc tile3 is gemmini + new gemmini.LeanGemminiConfig ++ // rerocc tile2 is gemmini + new gemmini.LeanGemminiConfig ++ // rerocc tile1 is gemmini + new gemmini.LeanGemminiConfig ++ // rerocc tile0 is gemmini + new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // 4 rocket cores + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala index 5ef76b75..c29b05d3 100644 --- a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala @@ -43,3 +43,17 @@ class WithMultiRoCCGemmini[T <: Data : Arithmetic, U <: Data, V <: Data]( })) } }) + +class WithAccumulatorRoCC(op: OpcodeSet = OpcodeSet.custom1) extends Config((site, here, up) => { + case BuildRoCC => up(BuildRoCC) ++ Seq((p: Parameters) => { + val accumulator = LazyModule(new AccumulatorExample(op, n = 4)(p)) + accumulator + }) +}) + +class WithCharacterCountRoCC(op: OpcodeSet = OpcodeSet.custom2) extends Config((site, here, up) => { + case BuildRoCC => up(BuildRoCC) ++ Seq((p: Parameters) => { + val counter = LazyModule(new CharacterCountExample(op)(p)) + counter + }) +}) diff --git a/generators/rerocc b/generators/rerocc index 78a29b0f..61751c3c 160000 --- a/generators/rerocc +++ b/generators/rerocc @@ -1 +1 @@ -Subproject commit 78a29b0f885deef1a99fb071dd6feeb7b65702b9 +Subproject commit 61751c3c23f6f7435cc264d32757956351cdb72a From 4f1dd4e1952a8976a38f833bd3552bca11673a61 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 5 Feb 2024 11:15:22 -0800 Subject: [PATCH 17/51] Add rerocc to tests --- .github/scripts/defaults.sh | 3 ++- .github/scripts/run-tests.sh | 4 ++++ .github/workflows/chipyard-run-tests.yml | 24 ++++++++++++++++++++++++ 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 124bdd3f..d76d7a32 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -30,7 +30,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache declare -A grouping grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle" grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet" -grouping["group-accels"]="chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb" +grouping["group-accels"]="chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc" grouping["group-constellation"]="chipyard-constellation" grouping["group-tracegen"]="tracegen tracegen-boomv3 tracegen-boomv4" grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters" @@ -72,6 +72,7 @@ mapping["chipyard-nomem-scratchpad"]=" CONFIG=MMIOScratchpadOnlyRocketConfig" mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig" mapping["chipyard-clusters"]=" CONFIG=ClusteredRocketConfig verilog" mapping["chipyard-aes256ecb"]=" CONFIG=AES256ECBRocketConfig" +mapping["chipyard-rerocc"]=" CONFIG=ReRoCCTestConfig" mapping["constellation"]=" SUB_PROJECT=constellation" mapping["firesim"]="TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig" diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index 31fea5d6..90fe0687 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -127,6 +127,10 @@ case $1 in make -C $LOCAL_CHIPYARD_DIR/tests run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv LOADMEM=1 ;; + chipyard-rerocc) + make -C $LOCAL_CHIPYARD_DIR/generators/rerocc/tests + run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/rerocc/tests/rerocc.riscv LOADMEM=1 + ;; tracegen) run_tracegen ;; diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 0b644888..24654306 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -777,6 +777,29 @@ jobs: group-key: "group-peripherals" project-key: "chipyard-llcchiplet" + chipyard-rerocc-run-tests: + name: chipyard-rerocc-run-tests + needs: prepare-chipyard-accels + runs-on: as4 + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v3 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Run tests + uses: ./.github/actions/run-tests + with: + group-key: "group-accels" + project-key: "chipyard-rerocc" + chipyard-gemmini-run-tests: name: chipyard-gemmini-run-tests needs: prepare-chipyard-accels @@ -1143,6 +1166,7 @@ jobs: chipyard-tethered-run-tests, chipyard-symmetric-run-tests, chipyard-llcchiplet-run-tests, + chipyard-rerocc-run-tests, chipyard-gemmini-run-tests, chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests, chipyard-prefetchers-run-tests, From e50adecd31bb797ad43e13ceff042dafd6bf02ee Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 29 May 2024 16:21:31 -0700 Subject: [PATCH 18/51] Bump rerocc --- generators/rerocc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/rerocc b/generators/rerocc index 61751c3c..a22dce62 160000 --- a/generators/rerocc +++ b/generators/rerocc @@ -1 +1 @@ -Subproject commit 61751c3c23f6f7435cc264d32757956351cdb72a +Subproject commit a22dce622db350e4a159ed90cf83d00782ed8187 From 2d2abed586b27874ba425e8eaffd47a7e579fd60 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 30 May 2024 13:38:00 -0700 Subject: [PATCH 19/51] Name all the generated ClockDomains --- .../chipyard/src/main/scala/clocking/HasChipyardPRCI.scala | 3 ++- generators/rocket-chip | 2 +- generators/rocket-chip-blocks | 2 +- generators/testchipip | 2 +- 4 files changed, 5 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index 9b140e20..d4b36b50 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -37,7 +37,8 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement // Set up clock domain private val tlbus = locateTLBusWrapper(prciParams.slaveWhere) - val prci_ctrl_domain = tlbus.generateSynchronousDomain.suggestName("chipyard_prcictrl_domain") + val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl") + .suggestName("chipyard_prcictrl_domain") val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } } prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar diff --git a/generators/rocket-chip b/generators/rocket-chip index a2356842..3cec0f0d 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit a2356842423c884863140745f686ec81d3544d07 +Subproject commit 3cec0f0dee432d6bb2da5ce6aa1142474807ff86 diff --git a/generators/rocket-chip-blocks b/generators/rocket-chip-blocks index 2fc961f3..c667be9b 160000 --- a/generators/rocket-chip-blocks +++ b/generators/rocket-chip-blocks @@ -1 +1 @@ -Subproject commit 2fc961f356b1104a34567adeefa9e3666940643f +Subproject commit c667be9bb32f25e52516e71cd1ded58290ac5993 diff --git a/generators/testchipip b/generators/testchipip index 104df6a8..7a30dc73 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 104df6a81fd989cd4cad69b699894664fcf93c05 +Subproject commit 7a30dc737d0d93e1e1926d56f7361d4b70ff5fe7 From 28b157c21621013a1631e70ed78acd0631a2067d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 6 Jun 2024 17:41:44 -0700 Subject: [PATCH 20/51] Remove firesim build.sbt from our SBT dependencies We don't depend on firesim's build.sbt anymore --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index e1120061..ce4ee2af 100644 --- a/common.mk +++ b/common.mk @@ -93,7 +93,7 @@ TAPEOUT_SOURCE_DIRS = $(addprefix $(base_dir)/,tools/tapeout) TAPEOUT_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(TAPEOUT_SOURCE_DIRS),$(SCALA_EXT)) TAPEOUT_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(TAPEOUT_SOURCE_DIRS),$(VLOG_EXT)) # This assumes no SBT meta-build sources -SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) +SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators tools) SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties ######################################################################################### From e1f37c0d3fb72cf927e86d0a06b00466f151a1d5 Mon Sep 17 00:00:00 2001 From: Brandon Michael Whitchurch Date: Tue, 11 Jun 2024 11:32:56 -0700 Subject: [PATCH 21/51] add upper bound for python version to avoid incompatible packages --- conda-reqs/chipyard-extended.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/conda-reqs/chipyard-extended.yaml b/conda-reqs/chipyard-extended.yaml index a1e87d4b..cf0b4320 100644 --- a/conda-reqs/chipyard-extended.yaml +++ b/conda-reqs/chipyard-extended.yaml @@ -30,7 +30,7 @@ dependencies: - bison - flex - expat - - python>=3.9 + - python>=3.9,<3.11 - bc - unzip - patch From 5e8a7469284d41f71305e38fff0af08550964ea3 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Wed, 12 Jun 2024 09:56:25 -0700 Subject: [PATCH 22/51] make: Remove obsolete args rom dependency --- common.mk | 2 +- variables.mk | 4 ---- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/common.mk b/common.mk index 7c9bd0c0..539beae9 100644 --- a/common.mk +++ b/common.mk @@ -22,7 +22,7 @@ HELP_COMPILATION_VARIABLES += \ " MFC_BASE_LOWERING_OPTIONS = override lowering options to pass to the MLIR FIRRTL compiler" \ " ASPECTS = comma separated list of Chisel aspect flows to run (e.x. chipyard.upf.ChipTopUPFAspect)" -EXTRA_GENERATOR_REQS ?= $(BOOTROM_TARGETS) $(ARGSROM_TARGETS) +EXTRA_GENERATOR_REQS ?= $(BOOTROM_TARGETS) EXTRA_SIM_CXXFLAGS ?= EXTRA_SIM_LDFLAGS ?= EXTRA_SIM_SOURCES ?= diff --git a/variables.mk b/variables.mk index 9878590a..7f6f4523 100644 --- a/variables.mk +++ b/variables.mk @@ -210,10 +210,6 @@ EXT_INCDIRS ?= BOOTROM_FILES ?= bootrom.rv64.img bootrom.rv32.img bootrom.radiance.rv32.img BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES)) -# custom *.bin argument files needed for Radiance -ARGSROM_FILES ?= args.bin op_a.bin op_b.bin -ARGSROM_TARGETS ?= $(addprefix $(base_dir)/sims/, $(ARGSROM_FILES)) - # files that contain lists of files needed for VCS or Verilator simulation SIM_FILE_REQS = sim_files ?= $(build_dir)/sim_files.f From 9a2d37e02b5a4eb0460a59713e36d94f75e6e3f7 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Wed, 12 Jun 2024 09:57:20 -0700 Subject: [PATCH 23/51] common.mk: Add run-binary-as-background target Instead of taking up the current interactive shell, this spawns an asynchronous process and relinquishes the shell back to user. Makes it easy to run multiple sims. TODO Currently only done for run-binary-debug --- common.mk | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/common.mk b/common.mk index 539beae9..e620f31a 100644 --- a/common.mk +++ b/common.mk @@ -350,7 +350,9 @@ run-binaries-fast: check-binaries $(addsuffix .run.fast,$(wildcard $(BINARIES))) # run simulator with as much debug info as possible run-binary-debug: check-binary $(BINARY).run.debug +run-binary-debug-bg: check-binary $(BINARY).run.debug.bg run-binaries-debug: check-binaries $(addsuffix .run.debug,$(wildcard $(BINARIES))) +run-binaries-debug-bg: check-binaries $(addsuffix .run.debug.bg,$(wildcard $(BINARIES))) %.run.debug: %.check-exists $(SIM_DEBUG_PREREQ) | $(output_dir) if [ "$*" != "none" ]; then riscv64-unknown-elf-objdump -D -S $* > $(call get_sim_out_name,$*).dump ; fi @@ -364,6 +366,19 @@ run-binaries-debug: check-binaries $(addsuffix .run.debug,$(wildcard $(BINARIES) $(BINARY_ARGS) \ >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log) +%.run.debug.bg: %.check-exists $(SIM_DEBUG_PREREQ) | $(output_dir) + if [ "$*" != "none" ]; then riscv64-unknown-elf-objdump -D -S $* > $(call get_sim_out_name,$*).dump ; fi + (set -o pipefail && $(NUMA_PREFIX) $(sim_debug) \ + $(PERMISSIVE_ON) \ + $(call get_common_sim_flags,$*) \ + $(VERBOSE_FLAGS) \ + $(call get_waveform_flag,$(call get_sim_out_name,$*)) \ + $(PERMISSIVE_OFF) \ + $* \ + $(BINARY_ARGS) \ + >(spike-dasm > $(call get_sim_out_name,$*).out) >$(call get_sim_out_name,$*).log \ + & echo "PID=$$!") + run-fast: run-asm-tests-fast run-bmark-tests-fast ######################################################################################### From 4fdc224c48177eed913379f8d98eaabfee7d7faa Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Jun 2024 11:11:27 -0700 Subject: [PATCH 24/51] Fix uniquify script for new firtool --- common.mk | 1 + scripts/uniquify-module-names.py | 8 +++++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/common.mk b/common.mk index e1120061..7f1b9669 100644 --- a/common.mk +++ b/common.mk @@ -218,6 +218,7 @@ $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILEL --model-hier-json $(MFC_MODEL_HRCHY_JSON) \ --top-hier-json $(MFC_TOP_HRCHY_JSON) \ --in-all-filelist $(MFC_FILELIST) \ + --in-bb-filelist $(MFC_BB_MODS_FILELIST) \ --dut $(TOP) \ --model $(MODEL) \ --target-dir $(GEN_COLLATERAL_DIR) \ diff --git a/scripts/uniquify-module-names.py b/scripts/uniquify-module-names.py index d2131c33..5c6a9613 100755 --- a/scripts/uniquify-module-names.py +++ b/scripts/uniquify-module-names.py @@ -11,6 +11,7 @@ parser = argparse.ArgumentParser(description="") parser.add_argument("--model-hier-json", type=str, required=True, help="Path to hierarchy JSON emitted by firtool. Must include DUT as a module.") parser.add_argument("--top-hier-json", type=str, required=True, help="Path to hierarchy JSON emitted by firtool. Must include DUT as a module.") parser.add_argument('--in-all-filelist', type=str, required=True, help='Path to input filelist that has all modules (relative paths).') +parser.add_argument('--in-bb-filelist', type=str, required=True, help='Path to input blackbox filelist') parser.add_argument("--dut", type=str, required=True, help="Name of the DUT module.") parser.add_argument("--model", type=str, required=True, help="Name of the Model module.") parser.add_argument('--out-dut-filelist', type=str, required=True, help='Path to output filelist including all modules under the DUT.') @@ -57,8 +58,8 @@ def get_modules_in_verilog_file(file): module_names.append(words[1].replace("(", "").replace(")", "").replace(";", "")) return module_names -def get_modules_in_filelist(verilog_module_filename, cc_filelist): - with open(args.in_all_filelist) as fl: +def get_modules_in_filelist(filelist, verilog_module_filename, cc_filelist): + with open(filelist) as fl: lines = fl.readlines() for line in lines: path = line.strip() @@ -186,7 +187,8 @@ def uniquify_modules_under_model(modules_under_model, common_modules, verilog_mo def main(): verilog_module_filename = dict() cc_filelist = list() - get_modules_in_filelist(verilog_module_filename, cc_filelist) + get_modules_in_filelist(args.in_all_filelist, verilog_module_filename, cc_filelist) + get_modules_in_filelist(args.in_bb_filelist , verilog_module_filename, cc_filelist) modules_under_model = get_modules_under_hier(args.model_hier_json, args.dut) modules_under_top = get_modules_under_hier(args.top_hier_json) From a15fb7ff3d240f4a723ec8be1a9feda5659e9bc9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Jun 2024 11:36:55 -0700 Subject: [PATCH 25/51] Remove unused thin-client stuff --- common.mk | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/common.mk b/common.mk index ce4ee2af..431238d7 100644 --- a/common.mk +++ b/common.mk @@ -96,16 +96,6 @@ TAPEOUT_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(TAPEOUT_SOURCE_DIRS SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators tools) SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties -######################################################################################### -# SBT Server Setup (start server / rebuild proj. defs. if SBT_SOURCES change) -######################################################################################### -$(SBT_THIN_CLIENT_TIMESTAMP): $(SBT_SOURCES) -ifneq (,$(wildcard $(SBT_THIN_CLIENT_TIMESTAMP))) - cd $(base_dir) && $(SBT) "reload" - touch $@ -else - cd $(base_dir) && $(SBT) "exit" -endif ######################################################################################### # copy over bootrom files From dcb3d24b08a3ef83b4e8ae3d95c1936cb30650a0 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Jun 2024 11:37:13 -0700 Subject: [PATCH 26/51] Log CIRCT output into a log file --- common.mk | 7 ++++--- variables.mk | 1 + 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/common.mk b/common.mk index 431238d7..fdb2bde2 100644 --- a/common.mk +++ b/common.mk @@ -169,7 +169,8 @@ SFC_MFC_TARGETS = \ $(MFC_MODEL_SMEMS_JSON) \ $(MFC_FILELIST) \ $(MFC_BB_MODS_FILELIST) \ - $(GEN_COLLATERAL_DIR) + $(GEN_COLLATERAL_DIR) \ + $(FIRTOOL_LOG_FILE) MFC_BASE_LOWERING_OPTIONS ?= emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,disallowPortDeclSharing,locationInfoStyle=wrapInAtSquareBracket @@ -184,7 +185,7 @@ endif $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS) rm -rf $(GEN_COLLATERAL_DIR) - firtool \ + (set -o pipefail && firtool \ --format=fir \ --export-module-hierarchy \ --verify-each=true \ @@ -198,7 +199,7 @@ $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS) --annotation-file=$(FINAL_ANNO_FILE) \ --split-verilog \ -o $(GEN_COLLATERAL_DIR) \ - $(FIRRTL_FILE) + $(FIRRTL_FILE) |& tee $(FIRTOOL_LOG_FILE)) $(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler touch $(MFC_BB_MODS_FILELIST) # if there are no BB's then the file might not be generated, instead always generate it # DOC include end: FirrtlCompiler diff --git a/variables.mk b/variables.mk index ffb96d2f..5dfee196 100644 --- a/variables.mk +++ b/variables.mk @@ -154,6 +154,7 @@ TAPEOUT_CLASSPATH ?= $(CLASSPATH_CACHE)/tapeout.jar FIRRTL_FILE ?= $(build_dir)/$(long_name).fir ANNO_FILE ?= $(build_dir)/$(long_name).anno.json CHISEL_LOG_FILE ?= $(build_dir)/$(long_name).chisel.log +FIRTOOL_LOG_FILE ?= $(build_dir)/$(long_name).firtool.log # chisel anno modification output MFC_EXTRA_ANNO_FILE ?= $(build_dir)/$(long_name).extrafirtool.anno.json From eee405331baf9b035abcc7344ff754f0444c044b Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 12 Jun 2024 13:46:00 -0700 Subject: [PATCH 27/51] Bump CIRCT submodule --- tools/circt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/circt b/tools/circt index 9e0c1696..481cb60a 160000 --- a/tools/circt +++ b/tools/circt @@ -1 +1 @@ -Subproject commit 9e0c1696f3caef4059c65774ad6b8efee91d9d9e +Subproject commit 481cb60add7358934414a3c6b396f5d29ad934fe From 316c41ea522edffd189604e360a1a9535ac92769 Mon Sep 17 00:00:00 2001 From: Brandon Whitchurch Date: Thu, 13 Jun 2024 08:19:27 -0700 Subject: [PATCH 28/51] fixes for insert includes - avoid infinite loop condition - follow pep8 style guide - encapsulate some functionality to decrease visual nesting --- scripts/insert-includes.py | 162 +++++++++++++++++++++++-------------- 1 file changed, 101 insertions(+), 61 deletions(-) diff --git a/scripts/insert-includes.py b/scripts/insert-includes.py index b939878a..6c77bb5d 100755 --- a/scripts/insert-includes.py +++ b/scripts/insert-includes.py @@ -1,80 +1,120 @@ #!/usr/bin/env python +""" +replaces a `include with the full include file. -# replaces a `include with the full include file. -# recursively replaces `include's until none are left -# -# args -# $1 - file to remove includes from -# $2 - file to write output to -# $3 - list of directories to search for includes in (note: NON-RECURSIVE must specify all dirs) -# includes are found relative to this path -# this is equivalent to something like +incdir+ +args +$1 - file which has includes to be replaced +$2 - file in which output will be written +$3 - list of directories to search for includes + (note: NON-RECURSIVE must specify all dirs) + includes are found relative to this path + this is equivalent to something like +incdir+ +""" -import sys -import re import os -import tempfile +import re import shutil +import sys +import tempfile -inVlog = sys.argv[1] -outVlog = sys.argv[2] -print("[INFO] Replaces includes from: " + str(inVlog)) -if inVlog == outVlog: - sys.exit("[ERROR] The input and output file cannot be the same.") +def print_info(msg): + """ + Print an info message. -# add directories to search list -incDirs = sys.argv[3:] -print("[INFO] Searching following dirs for includes: " + str(incDirs)) + Args: + msg (str): message to print + """ + print(f"[INFO] {msg}") -def process(inF, outF): - # open file - with open(inF, 'r') as inFile: - with open(outF, 'w') as outFile: - # for each include found, search through all dirs and replace if found, error if not - for num, line in enumerate(inFile, 1): + +def print_error(msg, critical=True): + """ + Print an error message. + + Args: + msg (str): message to print + critical (bool): whether to exit after printing the message + """ + if critical: + sys.exit(f"[ERROR] {msg}") + else: + print(f"[ERROR] {msg}") + + +def find_include(file_name, inc_dirs): + """ + Find the include file in the list of directories. + + Args: + file_name (str): include file name + inc_dirs (list): list of directories to search for includes + + Returns: + str: full path to the include file + """ + for d in inc_dirs: + inc_file_name = d + "/" + file_name + if os.path.exists(inc_file_name): + return inc_file_name + print_error(f"Include file {file_name} not found in {inc_dirs}") + return None + + +def process(in_fname, out_fname, inc_dirs=None): + """ + Replace include directives in a file with the full include file. + + Args: + in_fname (str): input file name + out_fname (str): output file name + inc_dirs (list): list of directories to search for includes + """ + with open(in_fname, "r", encoding="utf-8") as in_file: + with open(out_fname, "w", encoding="utf-8") as out_file: + # for each include found, search through all dirs + # and replace if found, error if not + for num, line in enumerate(in_file, 1): match = re.match(r"^ *`include +\"(.*)\"", line) if match and match.group(1) != "uvm_macros.svh": - print("[INFO] Replacing includes for {}".format(match.group(1))) + print_info( + f"Replacing includes for {match.group(1)}" + f" at line {num}" + ) # search for include and replace - found = False - for d in incDirs: - potentialIncFileName = d + "/" + match.group(1) - if os.path.exists(potentialIncFileName): - found = True - print("[INFO] Found missing include in {}".format(potentialIncFileName)) - with open(potentialIncFileName, 'r') as incFile: - for iline in incFile: - outFile.write(iline) - break + inc_file_name = find_include(match.group(1), inc_dirs) + with open(inc_file_name, "r", encoding="utf-8") as inc_file: + out_file.writelines(inc_file) - # must find something to include with - if not found: - sys.exit("[ERROR] Couldn't replace include \"" + str(match.group(1)) + "\" found on line " + str(num)) else: - outFile.write(line) + out_file.write(line) -inF = inVlog -while True: - # create a copy of the input - fd, temp_path = tempfile.mkstemp() - shutil.copy2(inF, temp_path) +def main(): + """ + Entry point for the script. - with open(temp_path, 'r') as inFile: - anyIncludes = False - for line in inFile: - match = re.match(r"^ *`include +\"(.*)\"", line) - if match: - anyIncludes = True - break + Args: + + """ + in_vlog = sys.argv[1] + out_vlog = sys.argv[2] - if anyIncludes: - process(temp_path, outVlog) - inF = outVlog - os.remove(temp_path) - else: - os.remove(temp_path) - break + if in_vlog == out_vlog: + sys.exit("[ERROR] The input and output file cannot be the same.") -print("[INFO] Success. Writing output to: " + str(outVlog)) + # add directories to search list + inc_dirs = sys.argv[3:] + print("[INFO] Replaces includes from: " + str(in_vlog)) + print("[INFO] Searching following dirs for includes: " + str(inc_dirs)) + + # make a copy of the input file + _, temp_path = tempfile.mkstemp() + shutil.copy2(in_vlog, temp_path) + process(temp_path, out_vlog, inc_dirs) + + print("[INFO] Success. Output written to: " + str(out_vlog)) + + +if __name__ == "__main__": + main() From feeab6b93be81ba1665910df462a4ae8cb81edda Mon Sep 17 00:00:00 2001 From: Brandon Whitchurch Date: Thu, 13 Jun 2024 08:35:37 -0700 Subject: [PATCH 29/51] add check for duplicate include directives --- scripts/insert-includes.py | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/scripts/insert-includes.py b/scripts/insert-includes.py index 6c77bb5d..bcf39a60 100755 --- a/scripts/insert-includes.py +++ b/scripts/insert-includes.py @@ -70,24 +70,29 @@ def process(in_fname, out_fname, inc_dirs=None): out_fname (str): output file name inc_dirs (list): list of directories to search for includes """ + replaced_includes = set() with open(in_fname, "r", encoding="utf-8") as in_file: with open(out_fname, "w", encoding="utf-8") as out_file: # for each include found, search through all dirs # and replace if found, error if not for num, line in enumerate(in_file, 1): match = re.match(r"^ *`include +\"(.*)\"", line) - if match and match.group(1) != "uvm_macros.svh": - print_info( - f"Replacing includes for {match.group(1)}" - f" at line {num}" - ) - # search for include and replace - inc_file_name = find_include(match.group(1), inc_dirs) - with open(inc_file_name, "r", encoding="utf-8") as inc_file: - out_file.writelines(inc_file) - - else: + if not match or match.group(1) == "uvm_macros.svh": + # copy the line as is out_file.write(line) + continue + if match.group(1) in replaced_includes: + print_info("Skipping duplicate include") + continue + + print_info( + f"Replacing includes for {match.group(1)}" f" at line {num}" + ) + # search for include and replace + inc_file_name = find_include(match.group(1), inc_dirs) + with open(inc_file_name, "r", encoding="utf-8") as inc_file: + out_file.writelines(inc_file) + replaced_includes.add(match.group(1)) def main(): From e4e49ef8985a76ffe2c13e0b451ba595a1d65d4a Mon Sep 17 00:00:00 2001 From: Brandon Whitchurch Date: Thu, 13 Jun 2024 09:13:05 -0700 Subject: [PATCH 30/51] use DFS to recursively search and expand includes in a single pass --- scripts/insert-includes.py | 54 ++++++++++++++++++++++---------------- 1 file changed, 32 insertions(+), 22 deletions(-) diff --git a/scripts/insert-includes.py b/scripts/insert-includes.py index bcf39a60..d29847c2 100755 --- a/scripts/insert-includes.py +++ b/scripts/insert-includes.py @@ -61,6 +61,36 @@ def find_include(file_name, inc_dirs): return None +def process_helper(in_fname, out_f, inc_dirs, replaced_includes): + """ + Helper function to DFS through include files and replace includes. + """ + print(f"DFS state: {replaced_includes}") + include_regex = re.compile(r"^ *`include +\"(.*)\"") + # slurp the input file. + # this avoids having a bunch of fds open during recursion + with open(in_fname, "r", encoding="utf-8") as in_file: + lines = in_file.readlines() + + for num, line in enumerate(lines, 1): + match = re.match(include_regex, line) + if not match or match.group(1) == "uvm_macros.svh": + # copy the line as is + out_f.write(line) + continue + if match.group(1) in replaced_includes: + print_info("Skipping duplicate include") + continue + + print_info( + f"Replacing includes for {match.group(1)}" f" at line {num}" + ) + # search for include and replace + inc_file_name = find_include(match.group(1), inc_dirs) + replaced_includes.add(match.group(1)) + process_helper(inc_file_name, out_f, inc_dirs, replaced_includes) + + def process(in_fname, out_fname, inc_dirs=None): """ Replace include directives in a file with the full include file. @@ -71,28 +101,8 @@ def process(in_fname, out_fname, inc_dirs=None): inc_dirs (list): list of directories to search for includes """ replaced_includes = set() - with open(in_fname, "r", encoding="utf-8") as in_file: - with open(out_fname, "w", encoding="utf-8") as out_file: - # for each include found, search through all dirs - # and replace if found, error if not - for num, line in enumerate(in_file, 1): - match = re.match(r"^ *`include +\"(.*)\"", line) - if not match or match.group(1) == "uvm_macros.svh": - # copy the line as is - out_file.write(line) - continue - if match.group(1) in replaced_includes: - print_info("Skipping duplicate include") - continue - - print_info( - f"Replacing includes for {match.group(1)}" f" at line {num}" - ) - # search for include and replace - inc_file_name = find_include(match.group(1), inc_dirs) - with open(inc_file_name, "r", encoding="utf-8") as inc_file: - out_file.writelines(inc_file) - replaced_includes.add(match.group(1)) + with open(out_fname, "w", encoding="utf-8") as out_file: + process_helper(in_fname, out_file, inc_dirs, replaced_includes) def main(): From ecd7c805a40b6aa42fcaf24b787cfbd11977b435 Mon Sep 17 00:00:00 2001 From: Brandon Whitchurch Date: Thu, 13 Jun 2024 09:18:44 -0700 Subject: [PATCH 31/51] remove debug print --- scripts/insert-includes.py | 1 - 1 file changed, 1 deletion(-) diff --git a/scripts/insert-includes.py b/scripts/insert-includes.py index d29847c2..22dd8e9d 100755 --- a/scripts/insert-includes.py +++ b/scripts/insert-includes.py @@ -65,7 +65,6 @@ def process_helper(in_fname, out_f, inc_dirs, replaced_includes): """ Helper function to DFS through include files and replace includes. """ - print(f"DFS state: {replaced_includes}") include_regex = re.compile(r"^ *`include +\"(.*)\"") # slurp the input file. # this avoids having a bunch of fds open during recursion From ca20f0b17a18e7f5469721f961e5595649231a0c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 19 Jun 2024 13:25:44 -0700 Subject: [PATCH 32/51] Bump FireMarshal --- software/firemarshal | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/firemarshal b/software/firemarshal index a98f1faf..87c9fd1d 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit a98f1faff6d11a0b4418d3a814cabd51c734c822 +Subproject commit 87c9fd1db339ca3987ebcac5df2f00587bb25dd2 From 069fc93689f086c04e1623ca30acd29fd460bbd8 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 19 Jun 2024 16:56:27 -0700 Subject: [PATCH 33/51] Bump FireMarshal + PK (Pk bumped to fix toolchain bump issues w/ linux) --- software/firemarshal | 2 +- toolchains/riscv-tools/riscv-pk | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/software/firemarshal b/software/firemarshal index 87c9fd1d..0c0cdfeb 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit 87c9fd1db339ca3987ebcac5df2f00587bb25dd2 +Subproject commit 0c0cdfeb269b37c3d10e5f21b84cd60c21457487 diff --git a/toolchains/riscv-tools/riscv-pk b/toolchains/riscv-tools/riscv-pk index e8e6b3aa..4f3debe4 160000 --- a/toolchains/riscv-tools/riscv-pk +++ b/toolchains/riscv-tools/riscv-pk @@ -1 +1 @@ -Subproject commit e8e6b3aaee44d43b48164fbd377864c3a682dbd3 +Subproject commit 4f3debe4d04f56d31089c1c716a27e2d5245e9a1 From d529844a9dd0c2aa36eed2b64d5fb3bc27def647 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 21 Jun 2024 11:30:43 -0700 Subject: [PATCH 34/51] Update ClockGroup aggregation error to be more descriptive --- .../chipyard/src/main/scala/clocking/ClockGroupCombiner.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala index 9b53cbef..9508e76f 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala @@ -48,9 +48,10 @@ class ClockGroupCombiner(implicit p: Parameters, v: ValName) extends LazyModule val name = combiners(i)._1 i = i + 1 require(g.size >= 1) + val names = g.map(_.name.getOrElse("unamed")) val takes = g.map(_.take).flatten require(takes.distinct.size <= 1, - s"Clock group $name has non-homogeneous requested ClockParameters $takes") + s"Clock group $name has non-homogeneous requested ClockParameters ${names.zip(takes)}") require(takes.size > 0, s"Clock group $name has no inheritable frequencies") (grouped ++ Seq(ClockSinkParameters(take = takes.headOption, name = Some(name))), r) From 0fddd3c69ed6dad8dc510eedf70165f968cedfa8 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 21 Jun 2024 17:18:34 -0700 Subject: [PATCH 35/51] Update checkpointing script --- scripts/generate-ckpt.sh | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/scripts/generate-ckpt.sh b/scripts/generate-ckpt.sh index 3795b041..fe42d997 100755 --- a/scripts/generate-ckpt.sh +++ b/scripts/generate-ckpt.sh @@ -13,6 +13,8 @@ usage() { echo " -i : Instructions after PC to take checkpoint at [default 0]" echo " -m : ISA to pass to spike for checkpoint generation [default rv64gc]" echo " -o : Output directory to store the checkpoint in. [default ...loadarch]" + echo " -r : Memory regions to pass to spike. Passed to spike's '-m' flag. [default starting at 0x80000000 with 256MiB]" + echo " -v : Verbose" exit "$1" } @@ -22,6 +24,8 @@ PC="0x80000000" INSNS=0 ISA="rv64gc" OUTPATH="" +MEMOVERRIDE="" +VERBOSE=0 while [ "$1" != "" ]; do case $1 in @@ -45,6 +49,11 @@ do -o ) shift OUTPATH=$1 ;; + -r ) + shift + MEMOVERRIDE=$1 ;; + -v ) + VERBOSE=1 ;; * ) error "Invalid option $1" usage 1 ;; @@ -52,7 +61,15 @@ do shift done -BASEMEM="$((0x80000000)):$((0x10000000))" +if [[ $VERBOSE -eq 1 ]] ; then + set -x +fi + +if [ -z "$MEMOVERRIDE" ] ; then + BASEMEM="$((0x80000000)):$((0x10000000))" +else + BASEMEM=$MEMOVERRIDE +fi SPIKEFLAGS="-p$NHARTS --pmpregions=0 --isa=$ISA -m$BASEMEM" BASENAME=$(basename -- $BINARY) @@ -138,3 +155,5 @@ rm -rf mem.0x80000000.bin riscv64-unknown-elf-ld -Tdata=0x80000000 -nmagic --defsym tohost=0x$TOHOST --defsym fromhost=0x$FROMHOST -o $LOADMEM_ELF $RAWMEM_ELF rm -rf $RAWMEM_ELF + +echo "Ensure that at minimum you have memory regions corresponding to $BASEMEM in downstream RTL tooling" From 2a9fe9bb67f6838d771c79ed024ebeb2fad2d036 Mon Sep 17 00:00:00 2001 From: joonho hwangbo Date: Sat, 22 Jun 2024 16:08:57 -0700 Subject: [PATCH 36/51] Add compress-acc (#1906) * Add compress-acc * Bump compress-acc, add ci * update compress-acc url to https * Add docs * url oops * Bump compress-acc * BUMP * Use loadmem for ci runs * Add width widget * Bump --- .github/scripts/check-commit.sh | 2 +- .github/scripts/defaults.sh | 3 ++- .github/scripts/run-tests.sh | 14 +++++++---- .github/workflows/chipyard-run-tests.yml | 24 +++++++++++++++++++ .gitmodules | 3 +++ build.sbt | 8 ++++++- docs/Generators/CompressAcc.rst | 6 +++++ docs/Generators/index.rst | 1 + .../scala/config/RoCCAcceleratorConfigs.scala | 5 ++++ generators/compress-acc | 1 + 10 files changed, 59 insertions(+), 8 deletions(-) create mode 100644 docs/Generators/CompressAcc.rst create mode 160000 generators/compress-acc diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index 1b859414..e906ac29 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -46,7 +46,7 @@ search () { } -submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc") +submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc") dir="generators" branches=("master" "main" "dev") search diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index d76d7a32..0533846a 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -30,7 +30,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache declare -A grouping grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle" grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet" -grouping["group-accels"]="chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc" +grouping["group-accels"]="chipyard-compressacc chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb chipyard-rerocc" grouping["group-constellation"]="chipyard-constellation" grouping["group-tracegen"]="tracegen tracegen-boomv3 tracegen-boomv4" grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters" @@ -41,6 +41,7 @@ declare -A mapping mapping["chipyard-rocket"]=" CONFIG=QuadChannelRocketConfig" mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig" mapping["chipyard-mempress"]=" CONFIG=MempressRocketConfig" +mapping["chipyard-compressacc"]=" CONFIG=ZstdCompressorRocketConfig" mapping["chipyard-prefetchers"]=" CONFIG=PrefetchingRocketConfig" mapping["chipyard-digitaltop"]=" TOP=DigitalTop" mapping["chipyard-manymmioaccels"]=" CONFIG=ManyMMIOAcceleratorRocketConfig" diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index 90fe0687..6855e15a 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -72,7 +72,7 @@ case $1 in run_bmark ;; chipyard-prefetchers) - run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv + run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv LOADMEM=1 ;; rocketchip) run_bmark @@ -81,13 +81,17 @@ case $1 in GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests rm -rf $GEMMINI_SOFTWARE_DIR/riscv-tests cd $LOCAL_SIM_DIR - run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal - run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal - run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal + run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal LOADMEM=1 + run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal LOADMEM=1 + run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal LOADMEM=1 ;; chipyard-mempress) (cd $LOCAL_CHIPYARD_DIR/generators/mempress/software/src && make) - run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/mempress/software/src/mempress-rocc.riscv + run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/mempress/software/src/mempress-rocc.riscv LOADMEM=1 + ;; + chipyard-compressacc) + (cd $LOCAL_CHIPYARD_DIR/generators/compress-acc/software-zstd/compress && ./build-hcb-single-file.sh) + run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/compress-acc/software-zstd/compress/009987_cl0_ws12.riscv LOADMEM=1 ;; chipyard-manymmioaccels) make -C $LOCAL_CHIPYARD_DIR/tests diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 24654306..d86c75c9 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -892,6 +892,29 @@ jobs: group-key: "group-accels" project-key: "chipyard-mempress" + chipyard-compressacc-run-tests: + name: chipyard-compressacc-run-tests + needs: prepare-chipyard-accels + runs-on: as4 + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v3 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Run tests + uses: ./.github/actions/run-tests + with: + group-key: "group-accels" + project-key: "chipyard-compressacc" + tracegen-boomv3-run-tests: name: tracegen-boomv3-run-tests @@ -1171,6 +1194,7 @@ jobs: chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests, chipyard-prefetchers-run-tests, chipyard-mempress-run-tests, + chipyard-compressacc-run-tests, chipyard-constellation-run-tests, tracegen-boomv3-run-tests, tracegen-boomv4-run-tests, diff --git a/.gitmodules b/.gitmodules index c24ded76..6ff8ac86 100644 --- a/.gitmodules +++ b/.gitmodules @@ -145,3 +145,6 @@ [submodule "generators/rerocc"] path = generators/rerocc url = https://github.com/ucb-bar/rerocc.git +[submodule "generators/compress-acc"] + path = generators/compress-acc + url = https://github.com/ucb-bar/compress-acc.git diff --git a/build.sbt b/build.sbt index 36bf7742..0976a5e6 100644 --- a/build.sbt +++ b/build.sbt @@ -173,7 +173,8 @@ lazy val chipyard = (project in file("generators/chipyard")) .dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache, dsptools, rocket_dsp_utils, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, - constellation, mempress, barf, shuttle, caliptra_aes, rerocc) + constellation, mempress, barf, shuttle, caliptra_aes, rerocc, + compressacc) .settings(libraryDependencies ++= rocketLibDeps.value) .settings( libraryDependencies ++= Seq( @@ -183,6 +184,11 @@ lazy val chipyard = (project in file("generators/chipyard")) .settings(commonSettings) .settings(Compile / unmanagedSourceDirectories += file(stageDir)) +lazy val compressacc = (project in file("generators/compress-acc")) + .dependsOn(rocketchip) + .settings(libraryDependencies ++= rocketLibDeps.value) + .settings(commonSettings) + lazy val mempress = (project in file("generators/mempress")) .dependsOn(rocketchip) .settings(libraryDependencies ++= rocketLibDeps.value) diff --git a/docs/Generators/CompressAcc.rst b/docs/Generators/CompressAcc.rst new file mode 100644 index 00000000..b18b4709 --- /dev/null +++ b/docs/Generators/CompressAcc.rst @@ -0,0 +1,6 @@ +CompressAcc +==================================== + +We have (de)compression accelerators for two major compression algorithms : Snappy(`Snappy Github `__) and ZStd(`ZStd Github `__). + +For more information, check out the CDPU paper: `CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems `__ . diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 88d9ee2a..d55dce0c 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -33,4 +33,5 @@ so changes to the generators themselves will automatically be used when building Sodor Shuttle Mempress + CompressAcc Prefetchers diff --git a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala index 91ee7c15..960872b1 100644 --- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala @@ -67,3 +67,8 @@ class ReRoCCManyGemminiConfig extends Config( new gemmini.LeanGemminiConfig ++ // rerocc tile0 is gemmini new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // 4 rocket cores new chipyard.config.AbstractConfig) + +class ZstdCompressorRocketConfig extends Config( + new compressacc.WithZstdCompressor ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig) diff --git a/generators/compress-acc b/generators/compress-acc new file mode 160000 index 00000000..580fc99a --- /dev/null +++ b/generators/compress-acc @@ -0,0 +1 @@ +Subproject commit 580fc99a8de7e6965c5bc9f08945bc854d7d2a0c From 3ac74f0b60f743b8183f2bfd5ccb0c20c9908927 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 6 Jun 2024 11:32:47 -0700 Subject: [PATCH 37/51] Bump firesim for modern testchipip --- generators/testchipip | 2 +- sims/firesim | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/testchipip b/generators/testchipip index 7a30dc73..b85f5ac0 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 7a30dc737d0d93e1e1926d56f7361d4b70ff5fe7 +Subproject commit b85f5ac0464d16706000c6b1ef5b0c8556f84133 diff --git a/sims/firesim b/sims/firesim index c0117464..6137f5fe 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit c011746410594213fc229bd94cdeb17e506646eb +Subproject commit 6137f5fe452da71dbffab393ce34fb1bd39521c5 From 1e5893aa091c925ca5ec000900cce6de9d87ab9d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 6 Jun 2024 11:52:36 -0700 Subject: [PATCH 38/51] Bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 6137f5fe..23346f12 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 6137f5fe452da71dbffab393ce34fb1bd39521c5 +Subproject commit 23346f12dcfd76125dd1d5bec162b72bf9f7d97b From c1b869dfc03731622387331bdfe75bc96593dd48 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 6 Jun 2024 11:00:24 -0700 Subject: [PATCH 39/51] Update rocket-chip with modern diplomacy/prci packaging --- fpga/fpga-shells | 2 +- fpga/src/main/scala/vc707/Configs.scala | 3 ++- fpga/src/main/scala/vcu118/Configs.scala | 3 ++- generators/boom | 2 +- generators/chipyard/src/main/scala/SpikeTile.scala | 2 +- .../src/main/scala/config/MMIOAcceleratorConfigs.scala | 1 - .../chipyard/src/main/scala/config/MemorySystemConfigs.scala | 1 - generators/chipyard/src/main/scala/config/NoCConfigs.scala | 1 - .../src/main/scala/config/PeripheralDeviceConfigs.scala | 1 - .../src/main/scala/config/RoCCAcceleratorConfigs.scala | 1 - .../chipyard/src/main/scala/config/RocketConfigs.scala | 2 +- .../main/scala/config/fragments/PeripheralFragments.scala | 2 +- .../src/main/scala/config/fragments/SubsystemFragments.scala | 2 +- .../chipyard/src/main/scala/example/TutorialTile.scala | 2 +- generators/constellation | 2 +- generators/cva6 | 2 +- generators/firechip/src/main/scala/TargetConfigs.scala | 5 +++-- generators/ibex | 2 +- generators/icenet | 2 +- generators/riscv-sodor | 2 +- generators/rocket-chip | 2 +- generators/shuttle | 2 +- generators/testchipip | 2 +- tools/rocket-dsp-utils | 2 +- 24 files changed, 23 insertions(+), 25 deletions(-) diff --git a/fpga/fpga-shells b/fpga/fpga-shells index cdf3db20..2d36b0ab 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit cdf3db20f01abbb09937b77c992de1914f71956a +Subproject commit 2d36b0ab430fe3dc4cf378f378be21b925379110 diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala index d9fc1322..5b766107 100644 --- a/fpga/src/main/scala/vc707/Configs.scala +++ b/fpga/src/main/scala/vc707/Configs.scala @@ -6,7 +6,8 @@ import org.chipsalliance.cde.config.{Config, Parameters} import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} -import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} +import freechips.rocketchip.diplomacy.{RegionType, AddressSet} +import freechips.rocketchip.resources.{DTSModel, DTSTimebase} import freechips.rocketchip.tile.{XLen} import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams} diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index d9caa81d..afcbf7d4 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -6,7 +6,8 @@ import org.chipsalliance.cde.config.{Config, Parameters} import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem} import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG} import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated} -import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} +import freechips.rocketchip.diplomacy.{RegionType, AddressSet} +import freechips.rocketchip.resources.{DTSModel, DTSTimebase} import freechips.rocketchip.tile.{XLen} import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams} diff --git a/generators/boom b/generators/boom index 41c8fc9b..6a3ad0a1 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 41c8fc9bdfe68d0e30295cbaf764f2e69c36dbb8 +Subproject commit 6a3ad0a1d9ae659aba5aea78978ef1a7cb5dd163 diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala index 97866c50..6811be7a 100644 --- a/generators/chipyard/src/main/scala/SpikeTile.scala +++ b/generators/chipyard/src/main/scala/SpikeTile.scala @@ -14,7 +14,7 @@ import freechips.rocketchip.tilelink._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ -import freechips.rocketchip.prci.ClockSinkParameters +import freechips.rocketchip.prci._ case class SpikeCoreParams() extends CoreParams { val useVM = true diff --git a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala index fc6466ce..c1213d93 100644 --- a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala @@ -1,7 +1,6 @@ package chipyard import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // ------------------------------ // Configs with MMIO accelerators diff --git a/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala index 1b351266..fe99d5f1 100644 --- a/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala +++ b/generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala @@ -1,7 +1,6 @@ package chipyard import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // ------------------------------------------------------------ // Configs which demonstrate modifying the uncore memory system diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala index ac24d85c..ebd196c3 100644 --- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala @@ -1,7 +1,6 @@ package chipyard import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.diplomacy.{AsynchronousCrossing} import freechips.rocketchip.subsystem.{SBUS, MBUS} import constellation.channel._ diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala index fa74d9b8..c84427ad 100644 --- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala @@ -1,7 +1,6 @@ package chipyard import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.diplomacy.{AsynchronousCrossing} import freechips.rocketchip.subsystem.{MBUS} // --------------------------------------------------------- diff --git a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala index 960872b1..a654d70f 100644 --- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala @@ -1,7 +1,6 @@ package chipyard import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.diplomacy.{AsynchronousCrossing} // ------------------------------ // Configs with RoCC Accelerators diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 680129a3..c0ee4bba 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -1,7 +1,7 @@ package chipyard import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.diplomacy.{AsynchronousCrossing} +import freechips.rocketchip.prci.{AsynchronousCrossing} import freechips.rocketchip.subsystem.{InCluster} // -------------- diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 265be720..87229cb4 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -7,7 +7,7 @@ import chisel3.util.{log2Up} import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey, CLINTKey} import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI, JtagDTMKey, JtagDTMConfig} -import freechips.rocketchip.diplomacy.{AsynchronousCrossing} +import freechips.rocketchip.prci.{AsynchronousCrossing} import chipyard.stage.phases.TargetDirKey import freechips.rocketchip.subsystem._ import freechips.rocketchip.tile.{XLen} diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala index 8e16b26c..42899286 100644 --- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala @@ -2,7 +2,7 @@ package chipyard.config import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.subsystem._ -import freechips.rocketchip.diplomacy.{DTSTimebase} +import freechips.rocketchip.resources.{DTSTimebase} import sifive.blocks.inclusivecache.{InclusiveCachePortParameters} // Replaces the L2 with a broadcast manager for maintaining coherence diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 76b17273..f69ec864 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -14,7 +14,7 @@ import freechips.rocketchip.interrupts._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.amba.axi4._ -import freechips.rocketchip.prci.ClockSinkParameters +import freechips.rocketchip.prci._ // Example parameter class copied from CVA6, not included in documentation but for compile check only // If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure diff --git a/generators/constellation b/generators/constellation index 6664839b..5c9d2735 160000 --- a/generators/constellation +++ b/generators/constellation @@ -1 +1 @@ -Subproject commit 6664839b104a0d34adebfee13a0addc19efbde50 +Subproject commit 5c9d27359dcb2b144c99cc8e3e561979eb2bd905 diff --git a/generators/cva6 b/generators/cva6 index 9d1c1068..de4772f1 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 9d1c106834824ddb8052b7f60574b2b544b40395 +Subproject commit de4772f1d66cc6d4ef42e75f34c42eb7b941c8f0 diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 42f0b1d8..1793d32b 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -12,7 +12,8 @@ import freechips.rocketchip.rocket.DCacheParams import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams} import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey} -import freechips.rocketchip.diplomacy.{LazyModule, AsynchronousCrossing} +import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.prci.{AsynchronousCrossing} import testchipip.iceblk.{BlockDeviceKey, BlockDeviceConfig} import testchipip.cosim.{TracePortKey, TracePortParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} @@ -383,4 +384,4 @@ class FireSimLargeBoomSV39CospikeConfig extends Config( new WithDefaultMemModel ++ new WithFireSimConfigTweaks++ new chipyard.config.WithSV39 ++ - new chipyard.LargeBoomV3Config) \ No newline at end of file + new chipyard.LargeBoomV3Config) diff --git a/generators/ibex b/generators/ibex index 89c19c2d..8a43aa70 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit 89c19c2d7bc2523a0d9fb85e154bcaf2c1cc7665 +Subproject commit 8a43aa70da1c06f4d34ec8710a3d2ee7585948a5 diff --git a/generators/icenet b/generators/icenet index 969bc8f9..6fd35bf5 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 969bc8f9a00e4b11d243656f255761e04e10ccb9 +Subproject commit 6fd35bf5a28310c61671fce7309526b56d91e35d diff --git a/generators/riscv-sodor b/generators/riscv-sodor index ca043149..732cbe19 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit ca0431493ec35983388cb08bb203d5e12e9a32b2 +Subproject commit 732cbe1990e9ef55ba122664465b372744f2eaab diff --git a/generators/rocket-chip b/generators/rocket-chip index 3cec0f0d..4ac1529d 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 3cec0f0dee432d6bb2da5ce6aa1142474807ff86 +Subproject commit 4ac1529d982df90da6970c1425ec471e304ba4fb diff --git a/generators/shuttle b/generators/shuttle index 4792a1ab..799263c6 160000 --- a/generators/shuttle +++ b/generators/shuttle @@ -1 +1 @@ -Subproject commit 4792a1aba4e9f2d70e6f84587913f78c9e4c0340 +Subproject commit 799263c6180587670fe42de23f3338f1f218d87e diff --git a/generators/testchipip b/generators/testchipip index 7a30dc73..b85f5ac0 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 7a30dc737d0d93e1e1926d56f7361d4b70ff5fe7 +Subproject commit b85f5ac0464d16706000c6b1ef5b0c8556f84133 diff --git a/tools/rocket-dsp-utils b/tools/rocket-dsp-utils index c4c638da..6ee2309f 160000 --- a/tools/rocket-dsp-utils +++ b/tools/rocket-dsp-utils @@ -1 +1 @@ -Subproject commit c4c638da02351c701ff31e73aadd987baa7a2acc +Subproject commit 6ee2309f80a54b404795f227793d2a54e1dfadf8 From 760957a8cee4fa449d22d79e733a7217fde5398c Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 5 Jun 2024 13:06:11 -0700 Subject: [PATCH 40/51] Bump rc/components to improve module naming --- .../chipyard/src/main/scala/clocking/ClockBinders.scala | 6 +++--- .../src/main/scala/clocking/ClockGroupNamePrefixer.scala | 1 + .../chipyard/src/main/scala/clocking/HasChipyardPRCI.scala | 6 +++--- .../chipyard/src/main/scala/config/AbstractConfig.scala | 1 - generators/chipyard/src/main/scala/config/ChipConfigs.scala | 2 ++ .../chipyard/src/main/scala/config/NoCoreConfigs.scala | 2 +- generators/diplomacy | 2 +- generators/hardfloat | 2 +- generators/rocket-chip | 2 +- generators/rocket-chip-blocks | 2 +- generators/rocket-chip-inclusive-cache | 2 +- generators/testchipip | 2 +- 12 files changed, 16 insertions(+), 14 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index bcf2fb49..7ef9f922 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -27,9 +27,9 @@ class WithPLLSelectorDividerClockGenerator(enable: Boolean = true) extends Overr val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes, enable=enable)) } val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) } - clockDivider.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get } - clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get } - pllCtrl.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get } + clockDivider.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockDivider")) := system.prci_ctrl_bus.get } + clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("ClockSelector")) := system.prci_ctrl_bus.get } + pllCtrl.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus, Some("PLLCtrl")) := system.prci_ctrl_bus.get } system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala index 08d54acf..367386a1 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala @@ -28,6 +28,7 @@ class ClockGroupParameterModifier( sinkFn: ClockGroupSinkParameters => ClockGroupSinkParameters = { s => s })( implicit p: Parameters, v: ValName) extends LazyModule { val node = ClockGroupAdapterNode(sourceFn, sinkFn) + override def shouldBeInlined = true lazy val module = new LazyRawModuleImp(this) { (node.out zip node.in).map { case ((o, _), (i, _)) => (o.member.data zip i.member.data).foreach { case (oD, iD) => oD := iD } diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index d4b36b50..f1936d48 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -40,7 +40,7 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl") .suggestName("chipyard_prcictrl_domain") - val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } } + val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar(nameSuffix = Some("prcibus")) } } prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar := TLFIFOFixer(TLFIFOFixer.all) := TLBuffer() @@ -71,13 +71,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement } val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain { val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes)) - clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get + clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileClockGater")) := prci_ctrl_bus.get clock_gater } } val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain { val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes, tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil)) - reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get + reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileResetSetter")) := prci_ctrl_bus.get reset_setter } } diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 11d70982..ff65ad89 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -123,7 +123,6 @@ class AbstractConfig extends Config( new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */ new chipyard.config.WithSV48IfPossible ++ /** use sv48 if possible */ - // ================================================ // Set up power, reset and clocking // ================================================ diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index c34492a4..627babfa 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -7,6 +7,8 @@ import testchipip.soc.{OBUS} // A simple config demonstrating how to set up a basic chip in Chipyard class ChipLikeRocketConfig extends Config( + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + //================================== // Set up TestHarness //================================== diff --git a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala index 23da9700..5f376eaa 100644 --- a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala @@ -13,9 +13,9 @@ class NoCoresConfig extends Config( new chipyard.config.WithNoUART ++ new chipyard.config.WithNoTileClockGaters ++ new chipyard.config.WithNoTileResetSetters ++ - new chipyard.config.WithNoBusErrorDevices ++ new chipyard.config.WithNoDebug ++ new chipyard.config.WithNoPLIC ++ + new chipyard.config.WithNoBusErrorDevices ++ new chipyard.config.AbstractConfig) // A config that uses a empty chiptop module with no rocket-chip soc components diff --git a/generators/diplomacy b/generators/diplomacy index 055be698..6b7dc988 160000 --- a/generators/diplomacy +++ b/generators/diplomacy @@ -1 +1 @@ -Subproject commit 055be698f4ad55bf4a90b3d5e31d4344be5f788b +Subproject commit 6b7dc988a771ff21237b102fd02a1f2d2c2e7b72 diff --git a/generators/hardfloat b/generators/hardfloat index d93aa570..4225367e 160000 --- a/generators/hardfloat +++ b/generators/hardfloat @@ -1 +1 @@ -Subproject commit d93aa570806013dea479a92ba9bb33d1f2d4f69f +Subproject commit 4225367ed282aadd70f4cbd131f6959f4d00c502 diff --git a/generators/rocket-chip b/generators/rocket-chip index 4ac1529d..ea9979b1 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 4ac1529d982df90da6970c1425ec471e304ba4fb +Subproject commit ea9979b1c6e3cc078a6efe1f58012180753c5ec8 diff --git a/generators/rocket-chip-blocks b/generators/rocket-chip-blocks index c667be9b..c8c14f7b 160000 --- a/generators/rocket-chip-blocks +++ b/generators/rocket-chip-blocks @@ -1 +1 @@ -Subproject commit c667be9bb32f25e52516e71cd1ded58290ac5993 +Subproject commit c8c14f7b47c3c790022c293bc7e4309f5c5ed523 diff --git a/generators/rocket-chip-inclusive-cache b/generators/rocket-chip-inclusive-cache index 45d184f2..4aab5460 160000 --- a/generators/rocket-chip-inclusive-cache +++ b/generators/rocket-chip-inclusive-cache @@ -1 +1 @@ -Subproject commit 45d184f2fd1e2189d6302468e208a054b681caab +Subproject commit 4aab5460bd569b2142eb760e4772ea8db6998dc3 diff --git a/generators/testchipip b/generators/testchipip index b85f5ac0..5856bedf 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit b85f5ac0464d16706000c6b1ef5b0c8556f84133 +Subproject commit 5856bedf495188a95934969eac19a5fd9534bb0a From 193e712d2ff463821fbbeb63d709074483bbc852 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 25 Jun 2024 20:24:50 -0700 Subject: [PATCH 41/51] Bump chipyard build.sbt to 3.6.1 chisel3 --- build.sbt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index 0976a5e6..c0bc6d85 100644 --- a/build.sbt +++ b/build.sbt @@ -98,8 +98,8 @@ lazy val chisel6Settings = Seq( addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % "6.0.0" cross CrossVersion.full) ) lazy val chisel3Settings = Seq( - libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % "3.6.0"), - addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.6.0" cross CrossVersion.full) + libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % "3.6.1"), + addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.6.1" cross CrossVersion.full) ) lazy val chiselSettings = (if (chisel6) chisel6Settings else chisel3Settings) ++ Seq( From e7fc86cb78eec4efacb8fd4397ae8fb05ff8bff1 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 25 Jun 2024 20:31:07 -0700 Subject: [PATCH 42/51] Non-recursive clone of compress-acc (#1910) --- scripts/init-submodules-no-riscv-tools-nolog.sh | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index c81c95f1..dec397c3 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -74,6 +74,7 @@ cd "$RDIR" toolchains/libgloss \ generators/gemmini \ generators/rocket-chip \ + generators/compress-acc \ sims/firesim \ software/nvdla-workload \ software/coremark \ @@ -121,6 +122,9 @@ cd "$RDIR" # Non-recursive clone git submodule update --init generators/rocket-chip + # Non-recursive clone + git submodule update --init generators/compress-acc + # Minimal non-recursive clone to initialize sbt dependencies git submodule update --init sims/firesim git config --local submodule.sims/firesim.update none From 2bd10de4df4614da1225d81c4bc7ee9a9d452b41 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 25 Jun 2024 20:25:54 -0700 Subject: [PATCH 43/51] Bump firesim --- generators/chipyard/src/main/scala/config/ChipConfigs.scala | 2 -- sims/firesim | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index 627babfa..c34492a4 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -7,8 +7,6 @@ import testchipip.soc.{OBUS} // A simple config demonstrating how to set up a basic chip in Chipyard class ChipLikeRocketConfig extends Config( - new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - //================================== // Set up TestHarness //================================== diff --git a/sims/firesim b/sims/firesim index 23346f12..c95e7fbc 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 23346f12dcfd76125dd1d5bec162b72bf9f7d97b +Subproject commit c95e7fbc8d4de833874338b2a7f14ab4dbd979f1 From 6d8a07f11833bae5b12df77ea378db1c6d2ca669 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Wed, 26 Jun 2024 14:31:11 -0700 Subject: [PATCH 44/51] Bump rocket-gpu --- generators/rocket-gpu | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/rocket-gpu b/generators/rocket-gpu index 080bfd70..01eb6f15 160000 --- a/generators/rocket-gpu +++ b/generators/rocket-gpu @@ -1 +1 @@ -Subproject commit 080bfd706b09033a4996052d8ede25af00116507 +Subproject commit 01eb6f1559bb9653ad8318ebcc05795d27ae0b28 From 84265dda4f39bac1053be74ac55e7315d1e7fa6d Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Wed, 26 Jun 2024 14:31:52 -0700 Subject: [PATCH 45/51] Bump radiance --- generators/radiance | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/radiance b/generators/radiance index 5b4d3486..e1342e43 160000 --- a/generators/radiance +++ b/generators/radiance @@ -1 +1 @@ -Subproject commit 5b4d34864f06ea785a274b904e68516cb36d04ad +Subproject commit e1342e431cbab4502bc5308b34fbbe69a5a1a8dc From 5eda7997f4255cd9030232b2bac2b216b0335cd0 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Wed, 26 Jun 2024 17:09:10 -0700 Subject: [PATCH 46/51] Change RadianceSmem16KConfig to 4 cores --- .../chipyard/src/main/scala/config/RadianceConfigs.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala index c890e6af..7b0047ac 100644 --- a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala @@ -62,8 +62,8 @@ class RadianceClusterConfig extends Config( class RadianceClusterSmem16KConfig extends Config( new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 4, tileSize = 4) ++ - new radiance.subsystem.WithRadianceCores(2, location = InCluster(0), useVxCache = false) ++ - new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 16 << 10, numBanks = 4, numWords = 8, serializeUnaligned = false) ++ + new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), useVxCache = false) ++ + new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 16 << 10/*KBytes*/, numBanks = 4, numWords = 8, serializeUnaligned = false) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++ new radiance.subsystem.WithRadianceCluster(0) ++ From f24312322b5246e662cdab58c0980707debac410 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Wed, 26 Jun 2024 17:09:54 -0700 Subject: [PATCH 47/51] Add 1-core 1-Gemmini small cluster config --- .../src/main/scala/config/RadianceConfigs.scala | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala index 7b0047ac..0cbaed5a 100644 --- a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala @@ -54,7 +54,17 @@ class RadianceClusterConfig extends Config( new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++ new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), useVxCache = false) ++ // new radiance.subsystem.WithRadianceFrameBuffer(x"ff018000", 16, 0x8000, x"ff011000", "fb0") ++ - new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 64 << 10, numBanks = 4, numWords = 8, serializeUnaligned = true) ++ + new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 64 << 10/*KBytes*/, numBanks = 4, numWords = 8, serializeUnaligned = true) ++ + new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ + new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++ + new radiance.subsystem.WithRadianceCluster(0) ++ + new RadianceBaseConfig) + +class RadianceClusterSmallConfig extends Config( + // important to keep gemmini tile before RadianceCores to ensure radiance tile id is 0-indexed + new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 8, accSizeInKB = 16, tileSize = 8) ++ + new radiance.subsystem.WithRadianceCores(1, location = InCluster(0), useVxCache = false) ++ + new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 64 << 10/*KBytes*/, numBanks = 4, numWords = 8, serializeUnaligned = true) ++ new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++ new radiance.subsystem.WithVortexL1Banks(nBanks = 8)++ new radiance.subsystem.WithRadianceCluster(0) ++ From f91d8e3e589ea0c368761a1efd30b7755bc655eb Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Thu, 27 Jun 2024 17:16:55 -0700 Subject: [PATCH 48/51] Bump rocket-chip after merging --- generators/rocket-chip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/rocket-chip b/generators/rocket-chip index c6fa6b91..cd35968a 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit c6fa6b918d91ec053424bfdec3ba47177c4c1b1c +Subproject commit cd35968aa4a42045b89c66d0c8a8ba3592558542 From 02eedb898c321964d08bbe1373e696368b906d1a Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Thu, 27 Jun 2024 17:18:09 -0700 Subject: [PATCH 49/51] Fix module imports after rocket-chip bump --- .../chipyard/src/main/scala/config/CoalescerConfigs.scala | 2 +- .../chipyard/src/main/scala/config/RadianceConfigs.scala | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala b/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala index 58456bdd..c88d1635 100644 --- a/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala +++ b/generators/chipyard/src/main/scala/config/CoalescerConfigs.scala @@ -1,7 +1,7 @@ package chipyard import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.diplomacy.{AsynchronousCrossing} +import freechips.rocketchip.prci.AsynchronousCrossing class MemtraceCoreConfig extends Config( // Memtrace diff --git a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala index 0cbaed5a..8938f057 100644 --- a/generators/chipyard/src/main/scala/config/RadianceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RadianceConfigs.scala @@ -3,7 +3,8 @@ package chipyard import chipyard.config.AbstractConfig import chipyard.stage.phases.TargetDirKey import freechips.rocketchip.devices.tilelink.BootROMLocated -import freechips.rocketchip.diplomacy.{AsynchronousCrossing, BigIntHexContext} +import freechips.rocketchip.prci.AsynchronousCrossing +import freechips.rocketchip.resources.BigIntHexContext import freechips.rocketchip.subsystem._ import org.chipsalliance.cde.config.Config import radiance.memory._ From cc018c263f5781730ae50fca994406c55780f7bd Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Thu, 27 Jun 2024 17:19:10 -0700 Subject: [PATCH 50/51] Bump radiance with import fix --- generators/radiance | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/radiance b/generators/radiance index e1342e43..7aad800a 160000 --- a/generators/radiance +++ b/generators/radiance @@ -1 +1 @@ -Subproject commit e1342e431cbab4502bc5308b34fbbe69a5a1a8dc +Subproject commit 7aad800a2d7bf70a3b85384109e91d9d2e18ad19 From 9d0f02e34efdeecd63836a5d351e424e9420c572 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Fri, 19 Jul 2024 16:41:18 -0700 Subject: [PATCH 51/51] Bump radiance --- generators/radiance | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/radiance b/generators/radiance index 7aad800a..37fd0c62 160000 --- a/generators/radiance +++ b/generators/radiance @@ -1 +1 @@ -Subproject commit 7aad800a2d7bf70a3b85384109e91d9d2e18ad19 +Subproject commit 37fd0c6200d64f5b9091b133dd59dac393185886