From 7a39cbdddcd79d7e2257f6a78f48ca29f9ef7565 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Wed, 2 Oct 2019 00:34:29 -0700 Subject: [PATCH 01/37] bump down to innovus 18.1 --- docs/VLSI/Tutorial.rst | 5 +- vlsi/example-vlsi | 4 +- vlsi/example.yml | 2 +- vlsi/extra_libraries/example/ExampleDCO.gds | Bin 9536 -> 8556 bytes vlsi/extra_libraries/example/ExampleDCO.lef | 668 ++++++++++---------- vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- 7 files changed, 341 insertions(+), 342 deletions(-) diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst index 7c2e0d2f..de6e0166 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/Tutorial.rst @@ -54,8 +54,9 @@ Prerequisites * Genus, Innovus, and Calibre licenses * For ASAP7 specifically: - * Download the `ASAP7 PDK `__ tarball to a directory of choice but do not extract it + * Download the `ASAP7 PDK `__ tarball to a directory of choice but do not extract it. The tech plugin will extract and setup the PDK for you into a cache directory. * If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision. They may live outside ``extra_libraries`` at your discretion. + * Innovus version must be >= 15.2 or <= 18.1 (ISRs excluded). Initial Setup ------------- @@ -83,7 +84,7 @@ To elaborate the ``Sha3RocketConfig`` (Rocket Chip w/ the accelerator) and set u make buildfile MACROCOMPILER_MODE='--mode synflops' CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB -The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead. +The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead. Note this will dramatically increase synthesis runtimes if your design has a lot of caches. The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket Chip with the Sha3Accel module. diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index a17f4f0c..264d0d8d 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -36,9 +36,7 @@ def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool: set fp [open "{script_file}" "w"] puts -nonewline $fp "{script_text}" close $fp -if {{ [catch {{ exec python3 {script_file} }} msg] }} {{ - puts "$::errorInfo" -}} +exec python3 {script_file} '''.format(script_text=x.technology.scale_gds_script(x.output_gds_filename), script_file=os.path.join(x.run_dir, "gds_scale.py"))) return True diff --git a/vlsi/example.yml b/vlsi/example.yml index d8ca594b..3f8c0f23 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -124,7 +124,7 @@ synthesis.genus.version: "1813" vlsi.core.par_tool: "innovus" vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"] vlsi.core.par_tool_path_meta: "append" -par.innovus.version: "191" +par.innovus.version: "181" par.innovus.design_flow_effort: "standard" par.inputs.gds_merge: true # Calibre options diff --git a/vlsi/extra_libraries/example/ExampleDCO.gds b/vlsi/extra_libraries/example/ExampleDCO.gds index 9990b41cb9422c5e429e78f59005ab44cd04acc0..556f117ced6baa701af624cb5670c1bafdc0e7fe 100644 GIT binary patch literal 8556 zcmbuDUuc$99LLZ5I-i*>XZa@wCK&WjL+77T!D7}FN>FK%qRFP)TUoQov=j_Ffk6g_ z6&PgTpdy2c?5fLMb=`HBb=OsNSvP%u@7c#4ACG5e+YcT;_I-a}KJVF{$6j7nxn}dQ zTis}O{^{;sG{ncT1Yp?(@e_ogQuVKfm8CU$F4mU6;1){q@_wcl7_VapKyM zgKqW0OuLHP9gCc+?rXZoUA3g?oO^QV0{y9J_%@vVXZM7=MRKv@e&=rQ|2NNm zb^73k_`5^^4fIivhzc7G3#fK9wblpBY(HaHA{W)Lvk_eXOA8vPxd4K zGI?!Q=(6)eaxv>?j~*mX_9Oo)lWTf>@I!Jj>t~N1Bv1Au|7v+{*66bHLvk_eXOA8v zPxd4KT9a!Y_Q4Oy#jKw_dXPNXkNl6wYx9^cJ3k~BvwrsILGolj@~<KO`5ke)i}=@?<~q_sMJXoGv>*Bp0)O_UJ+KWIyunHo0bx z4}M54X8r8ZgXGD6xazt7~F{XY01xtR5{M-P%G`;q@8 zd2J5rvhzc7G3#fK9wblpBmW_jYYzM1hvZ_`&mKKUp6o~dqw?Au(`Dy}_`3~d2NpS;DPh7W#7F5cOXK7X@E50WSQ(fLowYcr86{p`_$Ie@|YU_jTF% zA-S0Kvquk-C;O5AqRBNM_~3`+V%Eaz1gaxv>?j~*mX_9OpwlWQh?@I!Jj>t~N1Bv1Au|5x(be51?G56Q)>pFMhz zJlT)@H%zYi&Idmv7qfo$=t1&iKk|Psug#CT?EH{i%=+1*2g#HD$bZx1nxB2}Lvk_e zXOA8vPxgbq@z+rM`@c39=&%3keZYoyynZ)7ug|8xIsX3fiPNs}`=oP5doSw`Op{!U z{h>eg`Df1ksh|IbpMu|L{@yFoH2>7=clFPqzpQ=!j`01d-ETIc{T%E)KyqX3Up~+N zntAra_s4U8|KayH_x{d#zW+V*>>rqC|HxeXUAMl!U)j_>Q9amj3tg9ei{JU1bIm@t zxThL9dG__zc(`Bk`_-gd+Ea~>of|yU8XY`wwD(v^>)yWGTbqhn-8I+dqSo@7YfDjU zRn4`vsP$0I^;A)7ZO!#`QR~r~YgNhQ~%)gX68&-X1-Ec5K}KXH)XreA<`j7M}BJ z%3FBWYbkHxd9SCuh5x>Mo$?m`8*?M&)k9M9bN(Ua)uU3( zBtA%*ipF9uA_Y<}{Xq#?WFJI&SbPXE0x1v?kqyL`r23wFe&4&7+w{Xd^U#Hz&z&W&G^Hb>CR|@J zrAaf*ck$fjB-+EdXm8*fY~cYs^x}B(piPmJ$Ti;#;9&SEcUT)6iFVaLjAN}&9R%C`#8_arfJCnP_i-@#e?UG+bQ6%sHNUvX`6-t;zeu88 z_1B3{ZV;bDuKDq8=ck-Tj%;*-cVKl;u2DQ`JHBGIn;--}QFC_af?^$&?pekwkRT=ln#PY#JsB3J!x z@yQ@i%*utCy{G@c-{FaZ#X|B(XRSmi%)(lK8alQH;PYg5uZe^`b)(pmx)gz z*ZksN&L_iAe4))%|El=pHRl&eFKyZ;Sg-0S+{i8V8`sB$(H!+D^^|y;p*2E`~ ztNtqS$%^L`ze*YrO&-VN&Id79_SI>V)e3J7v ziCp!!icb#VIkt#IuKL|L*j_)`ljtTQk*j_zK3Nu@M6UViynWr(N$2ewu8wV2eaz4H z`a_cQHi=yI4~S15l=G6vRiE=d$$6hduKG*m{3Pdn61nDc-X|Y!{-5r@#jEc8DX+QL zuh0J(|E&1rIq^y4>h$W^~fd~%`qBy!C!+;x7+ zd(JPAXjlD9;**!fCy}fE3GvA>@k!*Wzf*j2SbP$>>i3FI_K8m-SN(SJ$@$`w$TdIx z-SDQXW9~RVC34ljARaj`K8alQ4~tJ86Q4w``UB#VJH#iEXMMMRmhtbD9Q#Fvy`#q1 zoW$sTPEj;u4ch(Pz&I{&b2rtRWhQ7Q0 z|J(O@{X@z6e|rA1x4$&mW|7eTFTw3Q+Q;Pnm9eJA{~uass(@6*p!KOO`1nK{#cihC8Skl8tHb^5(GUBIa23{%&Q?r&XFO8>xPMQz)<3X$`AhG4Tn#FjPb&8H z41KV7M|EVzcf?+c`L1H-;f~aYs{JF?_dlv_+gl&myv+A{?lh{l+_PHYsYcbheXDJ1 zRP6=dYDXGXd(pSruGeha8tP9nbkEswba}%o@&j?vHx%m3&8#sF1JZJA#B)@|Ao?knpp7C7%(b^rT(;PbF*r M_3LG=TmnP$4-bSh761SM diff --git a/vlsi/extra_libraries/example/ExampleDCO.lef b/vlsi/extra_libraries/example/ExampleDCO.lef index ad850e2c..7a0594b7 100644 --- a/vlsi/extra_libraries/example/ExampleDCO.lef +++ b/vlsi/extra_libraries/example/ExampleDCO.lef @@ -6,374 +6,374 @@ MACRO ExampleDCO CLASS BLOCK ; ORIGIN 0 0 ; FOREIGN ExampleDCO 0 0 ; - SIZE 128.0 BY 128.0 ; + SIZE 129.536 BY 125.536 ; SYMMETRY X Y ; PIN VDD DIRECTION INOUT ; USE POWER ; - PORT - LAYER M7 ; - RECT 32.96 124.0 33.6 128.0 ; - END + PORT + LAYER M5 ; + RECT 10.608 121.536 11.088 125.536 ; + END END VDD PIN VSS DIRECTION INOUT ; USE GROUND ; - PORT + PORT LAYER M5 ; - RECT 93.12 124.0 93.76 128.0 ; - END + RECT 11.712 121.536 12.192 125.536 ; + END END VSS - PIN col_sel_b[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 113.28 4.0 113.664 ; - END - END col_sel_b[13] - PIN col_sel_b[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 107.648 4.0 108.032 ; - END - END col_sel_b[11] - PIN col_sel_b[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 90.752 4.0 91.136 ; - END - END col_sel_b[5] - PIN col_sel_b[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 110.464 4.0 110.848 ; - END - END col_sel_b[12] - PIN col_sel_b[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 104.832 4.0 105.216 ; - END - END col_sel_b[10] - PIN col_sel_b[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 102.016 4.0 102.4 ; - END - END col_sel_b[9] - PIN col_sel_b[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 99.2 4.0 99.584 ; - END - END col_sel_b[8] - PIN col_sel_b[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 96.384 4.0 96.768 ; - END - END col_sel_b[7] - PIN col_sel_b[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 93.568 4.0 93.952 ; - END - END col_sel_b[6] - PIN col_sel_b[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 87.936 4.0 88.32 ; - END - END col_sel_b[4] - PIN col_sel_b[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 85.12 4.0 85.504 ; - END - END col_sel_b[3] - PIN col_sel_b[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 82.304 4.0 82.688 ; - END - END col_sel_b[2] - PIN col_sel_b[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 79.488 4.0 79.872 ; - END - END col_sel_b[1] - PIN col_sel_b[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 76.672 4.0 77.056 ; - END - END col_sel_b[0] - PIN row_sel_b[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 71.04 4.0 71.424 ; - END - END row_sel_b[14] - PIN row_sel_b[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 68.224 4.0 68.608 ; - END - END row_sel_b[13] - PIN row_sel_b[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 65.408 4.0 65.792 ; - END - END row_sel_b[12] - PIN row_sel_b[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 62.592 4.0 62.976 ; - END - END row_sel_b[11] - PIN row_sel_b[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 59.776 4.0 60.16 ; - END - END row_sel_b[10] - PIN row_sel_b[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 56.96 4.0 57.344 ; - END - END row_sel_b[9] - PIN row_sel_b[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 54.144 4.0 54.528 ; - END - END row_sel_b[8] - PIN row_sel_b[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 51.328 4.0 51.712 ; - END - END row_sel_b[7] - PIN row_sel_b[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 48.512 4.0 48.896 ; - END - END row_sel_b[6] - PIN row_sel_b[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 45.696 4.0 46.08 ; - END - END row_sel_b[5] - PIN row_sel_b[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 42.88 4.0 43.264 ; - END - END row_sel_b[4] - PIN row_sel_b[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 40.064 4.0 40.448 ; - END - END row_sel_b[3] - PIN row_sel_b[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 37.248 4.0 37.632 ; - END - END row_sel_b[2] - PIN row_sel_b[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 34.432 4.0 34.816 ; - END - END row_sel_b[1] - PIN row_sel_b[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 31.616 4.0 32.0 ; - END - END row_sel_b[0] - PIN code_regulator[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 28.8 4.0 29.184 ; - END - END code_regulator[7] - PIN code_regulator[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 25.984 4.0 26.368 ; - END - END code_regulator[6] - PIN code_regulator[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 23.168 4.0 23.552 ; - END - END code_regulator[5] - PIN code_regulator[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 20.352 4.0 20.736 ; - END - END code_regulator[4] - PIN code_regulator[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 17.536 4.0 17.92 ; - END - END code_regulator[3] - PIN code_regulator[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 14.72 4.0 15.104 ; - END - END code_regulator[2] - PIN code_regulator[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 11.904 4.0 12.288 ; - END - END code_regulator[1] - PIN code_regulator[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 9.088 4.0 9.472 ; - END - END code_regulator[0] - PIN row_sel_b[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 73.856 4.0 74.24 ; - END - END row_sel_b[15] PIN dither DIRECTION INPUT ; USE SIGNAL ; - PORT + PORT LAYER M4 ; - RECT 0.0 6.272 4.0 6.656 ; - END + RECT 0.0 0.384 4.0 0.768 ; + END END dither + PIN row_sel_b[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 1.536 4.0 1.92 ; + END + END row_sel_b[0] + PIN row_sel_b[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 2.688 4.0 3.072 ; + END + END row_sel_b[1] + PIN row_sel_b[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 3.84 4.0 4.224 ; + END + END row_sel_b[2] + PIN row_sel_b[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 4.992 4.0 5.376 ; + END + END row_sel_b[3] + PIN row_sel_b[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 6.144 4.0 6.528 ; + END + END row_sel_b[4] + PIN row_sel_b[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 7.296 4.0 7.68 ; + END + END row_sel_b[5] + PIN row_sel_b[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 8.448 4.0 8.832 ; + END + END row_sel_b[6] + PIN row_sel_b[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 9.6 4.0 9.984 ; + END + END row_sel_b[7] + PIN row_sel_b[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 10.752 4.0 11.136 ; + END + END row_sel_b[8] + PIN row_sel_b[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 11.904 4.0 12.288 ; + END + END row_sel_b[9] + PIN row_sel_b[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 13.056 4.0 13.44 ; + END + END row_sel_b[10] + PIN row_sel_b[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 14.208 4.0 14.592 ; + END + END row_sel_b[11] + PIN row_sel_b[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 15.36 4.0 15.744 ; + END + END row_sel_b[12] + PIN row_sel_b[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 16.512 4.0 16.896 ; + END + END row_sel_b[13] + PIN row_sel_b[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 17.664 4.0 18.048 ; + END + END row_sel_b[14] + PIN row_sel_b[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 18.816 4.0 19.2 ; + END + END row_sel_b[15] + PIN col_sel_b[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 19.968 4.0 20.352 ; + END + END col_sel_b[0] + PIN col_sel_b[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 21.12 4.0 21.504 ; + END + END col_sel_b[1] + PIN col_sel_b[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 22.272 4.0 22.656 ; + END + END col_sel_b[2] + PIN col_sel_b[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 23.424 4.0 23.808 ; + END + END col_sel_b[3] + PIN col_sel_b[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 24.576 4.0 24.96 ; + END + END col_sel_b[4] + PIN col_sel_b[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 25.728 4.0 26.112 ; + END + END col_sel_b[5] + PIN col_sel_b[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 26.88 4.0 27.264 ; + END + END col_sel_b[6] + PIN col_sel_b[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 28.032 4.0 28.416 ; + END + END col_sel_b[7] + PIN col_sel_b[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 29.184 4.0 29.568 ; + END + END col_sel_b[8] + PIN col_sel_b[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 30.336 4.0 30.72 ; + END + END col_sel_b[9] + PIN col_sel_b[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 31.488 4.0 31.872 ; + END + END col_sel_b[10] + PIN col_sel_b[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 32.64 4.0 33.024 ; + END + END col_sel_b[11] + PIN col_sel_b[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 33.792 4.0 34.176 ; + END + END col_sel_b[12] + PIN col_sel_b[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 34.944 4.0 35.328 ; + END + END col_sel_b[13] + PIN code_regulator[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 36.096 4.0 36.48 ; + END + END code_regulator[0] + PIN code_regulator[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 37.248 4.0 37.632 ; + END + END code_regulator[1] + PIN code_regulator[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 38.4 4.0 38.784 ; + END + END code_regulator[2] + PIN code_regulator[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 39.552 4.0 39.936 ; + END + END code_regulator[3] + PIN code_regulator[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 40.704 4.0 41.088 ; + END + END code_regulator[4] + PIN code_regulator[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 41.856 4.0 42.24 ; + END + END code_regulator[5] + PIN code_regulator[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 43.008 4.0 43.392 ; + END + END code_regulator[6] + PIN code_regulator[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 44.16 4.0 44.544 ; + END + END code_regulator[7] PIN sleep_b DIRECTION INPUT ; USE SIGNAL ; - PORT - LAYER M5 ; - RECT 9.792 0.0 10.176 4.0 ; - END + PORT + LAYER M4 ; + RECT 0.0 45.312 4.0 45.696 ; + END END sleep_b PIN clock DIRECTION OUTPUT ; USE SIGNAL ; - PORT + PORT LAYER M4 ; - RECT 124.0 70.864 128.0 71.248 ; - END + RECT 125.536 0.384 129.536 0.768 ; + END END clock - OBS + OBS LAYER M1 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M2 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M3 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M4 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M5 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M6 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M7 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M8 ; - RECT 0.0 0.0 128.0 128.0 ; + RECT 0.0 0.0 129.536 121.536 ; LAYER M9 ; - RECT 0.0 0.0 128.0 128.0 ; + RECT 0.0 0.0 129.536 121.536 ; LAYER Pad ; - RECT 0.0 0.0 128.0 128.0 ; - END + RECT 0.0 0.0 129.536 121.536 ; + END END ExampleDCO END LIBRARY diff --git a/vlsi/hammer b/vlsi/hammer index 1b07b9a3..88226815 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 1b07b9a378c2936389b95f7ee1436e1f492d55e2 +Subproject commit 88226815243ae922ccd0d9d3810e3b6fcb6c97fd diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index 06ce365b..5e93f2e7 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit 06ce365b36e4b8520372968a5ef2a301afe8d5d6 +Subproject commit 5e93f2e72f5af06aaca0fbfa53e8d043d92e2341 From bb19f67aba60b2c5a99855708adca32a83397241 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Wed, 2 Oct 2019 18:50:34 -0700 Subject: [PATCH 02/37] fix innovus 18.1 not executing python script --- vlsi/example-vlsi | 7 ++++++- vlsi/hammer | 2 +- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index 264d0d8d..516ef588 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -24,6 +24,8 @@ def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: x.append(''' # TODO # Place custom TCL here +set_db route_design_bottom_routing_layer 2 +set_db route_design_top_routing_layer 7 ''') return True @@ -36,7 +38,10 @@ def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool: set fp [open "{script_file}" "w"] puts -nonewline $fp "{script_text}" close $fp -exec python3 {script_file} + +# Innovus <19.1 appends some bad LD_LIBRARY_PATHS, so remove them before executing python +set env(LD_LIBRARY_PATH) [join [lsearch -not -all -inline [split $env(LD_LIBRARY_PATH) ":"] "*INNOVUS*"] ":"] +python3 {script_file} '''.format(script_text=x.technology.scale_gds_script(x.output_gds_filename), script_file=os.path.join(x.run_dir, "gds_scale.py"))) return True diff --git a/vlsi/hammer b/vlsi/hammer index 88226815..d8fad54d 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 88226815243ae922ccd0d9d3810e3b6fcb6c97fd +Subproject commit d8fad54d125548e50bd65dffa3a53f001e412300 From dd79c54c965b926f6a44fcb7789ad3372ac7493f Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Wed, 2 Oct 2019 19:04:57 -0700 Subject: [PATCH 03/37] bump hammer --- vlsi/hammer | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/hammer b/vlsi/hammer index d8fad54d..b5024772 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit d8fad54d125548e50bd65dffa3a53f001e412300 +Subproject commit b50247729bc536522ae42e8adb5e38277095775b From f7d09957e907f50bfa2b4e4ac7422bd35f871f87 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Thu, 3 Oct 2019 10:34:23 -0700 Subject: [PATCH 04/37] Add warning directive for Mac/Windows warnings --- docs/Quick-Start.rst | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/docs/Quick-Start.rst b/docs/Quick-Start.rst index 542e3a30..ee7518c4 100644 --- a/docs/Quick-Start.rst +++ b/docs/Quick-Start.rst @@ -5,8 +5,10 @@ Requirements ------------------------------------------- Chipyard is developed and tested on Linux-based systems. -It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed; it is also recommended to install the RISC-V toolchain from ``brew``. -Working under Windows is not recommended. + +.. Warning:: It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed; it is also recommended to install the RISC-V toolchain from ``brew``. + +.. Warning:: Working under Windows is not recommended. Setting up the Chipyard Repo ------------------------------------------- From 4bf982ad09a699f5d8be2f44795de216147ddbb3 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Thu, 3 Oct 2019 20:30:03 +0000 Subject: [PATCH 05/37] sha3: Bump RTL for tutorial enhancements --- generators/sha3 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sha3 b/generators/sha3 index 83dd1955..b364cd36 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit 83dd1955a9a6f277addfbcc65394986e73fc03b2 +Subproject commit b364cd367ceb8636b8dbec3c46bf1aab1788b2c3 From 2dc8c7c143eeab3a02c9dc4a39ec48055aade020 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Thu, 3 Oct 2019 20:40:12 +0000 Subject: [PATCH 06/37] sha3: Update submodule URL The original URL should still redirect. --- .gitmodules | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 4c23765e..180a68bc 100644 --- a/.gitmodules +++ b/.gitmodules @@ -77,9 +77,9 @@ [submodule "tools/treadle"] path = tools/treadle url = https://github.com/freechipsproject/treadle.git -[submodule "generators/rocc-template"] +[submodule "generators/sha3"] path = generators/sha3 - url = https://github.com/ucb-bar/rocc-template.git + url = https://github.com/ucb-bar/sha3.git [submodule "tools/firrtl-interpreter"] path = tools/firrtl-interpreter url = https://github.com/freechipsproject/firrtl-interpreter.git From 41c560e5a8c20c831765fdc358c535880b4b078b Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Thu, 3 Oct 2019 18:47:04 -0400 Subject: [PATCH 07/37] Add symlink to firemarshal to software/firemarshal. Marshal still lives in firesim for now, but can be accessed from chipyard top. --- scripts/init-submodules-no-riscv-tools.sh | 27 ++++++++++++++++++----- sims/firesim | 2 +- software/firemarshal | 1 + 3 files changed, 23 insertions(+), 7 deletions(-) create mode 120000 software/firemarshal diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index e17b67ef..667f33b4 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -6,6 +6,18 @@ set -o pipefail RDIR=$(git rev-parse --show-toplevel) +NO_FIRESIM=false + +while test $# -gt 0 +do + case "$1" in + --no-firesim) + NO_FIRESIM=true; + ;; + esac + shift +done + # Ignore toolchain submodules cd "$RDIR" for name in toolchains/*/*/ ; do @@ -26,9 +38,12 @@ git config --unset submodule.vlsi/hammer-cadence-plugins.update git config --unset submodule.vlsi/hammer-synopsys-plugins.update git config --unset submodule.vlsi/hammer-mentor-plugins.update -# Renable firesim and init only the required submodules to provide -# all required scala deps, without doing a full build-setup -git config --unset submodule.sims/firesim.update -git submodule update --init sims/firesim -git -C sims/firesim submodule update --init sim/midas -git config submodule.sims/firesim.update none +if [ "NO_FIRESIM" = false ]; then + # Renable firesim and init only the required submodules to provide + # all required scala deps, without doing a full build-setup + git config --unset submodule.sims/firesim.update + git submodule update --init sims/firesim + git -C sims/firesim submodule update --init sim/midas + git -C sims/firesim submodule update --init --recursive sw/firesim-software + git config submodule.sims/firesim.update none +fi diff --git a/sims/firesim b/sims/firesim index 26ffba7c..ffe68ac7 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 26ffba7cbca2982fef6b221a7abbc51d5cdc4b62 +Subproject commit ffe68ac7f69795b2cccf7d9510facd5e2db4edc6 diff --git a/software/firemarshal b/software/firemarshal new file mode 120000 index 00000000..c1e20e80 --- /dev/null +++ b/software/firemarshal @@ -0,0 +1 @@ +../sims/firesim/sw/firesim-software/ \ No newline at end of file From dcddf2c842679dfdc819fbcb7371f84a0b9b16d2 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Thu, 3 Oct 2019 20:20:41 -0400 Subject: [PATCH 08/37] Fix typo in firesim initialization in init-submodules-no-riscv-tools.sh --- scripts/init-submodules-no-riscv-tools.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 667f33b4..da34adf0 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -38,7 +38,7 @@ git config --unset submodule.vlsi/hammer-cadence-plugins.update git config --unset submodule.vlsi/hammer-synopsys-plugins.update git config --unset submodule.vlsi/hammer-mentor-plugins.update -if [ "NO_FIRESIM" = false ]; then +if [ $NO_FIRESIM = false ]; then # Renable firesim and init only the required submodules to provide # all required scala deps, without doing a full build-setup git config --unset submodule.sims/firesim.update From e5713a4127d26e0a514b00e5731eb4b1badb9134 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Thu, 3 Oct 2019 20:36:37 -0400 Subject: [PATCH 09/37] Update docs to include path to FireMarshal --- docs/Software/FireMarshal.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/Software/FireMarshal.rst b/docs/Software/FireMarshal.rst index ecc23736..da529f13 100644 --- a/docs/Software/FireMarshal.rst +++ b/docs/Software/FireMarshal.rst @@ -1,5 +1,6 @@ FireMarshal ================= +``software/firemarshal`` FireMarshal is a workload generation tool for RISC-V based systems. It currently only supports the FireSim FPGA-accelerated simulation platform. From d1e3cc558bb21be8beb4a883a7ffcad00de9e157 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Fri, 4 Oct 2019 01:09:53 +0000 Subject: [PATCH 10/37] firechip: Add FireSimRocketChipSha3L2Config --- build.sbt | 2 +- generators/firechip/src/main/scala/TargetConfigs.scala | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index 05a80bba..4d747829 100644 --- a/build.sbt +++ b/build.sbt @@ -188,7 +188,7 @@ lazy val midas = ProjectRef(firesimDir, "midas") lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") lazy val firechip = (project in file("generators/firechip")) - .dependsOn(boom, icenet, testchipip, sifive_blocks, sifive_cache, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") + .dependsOn(boom, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, testGrouping in Test := isolateAllTests( (definedTests in Test).value ) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 0e31bb56..d88ffa25 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -138,6 +138,13 @@ class FireSimRocketChipOctaCoreConfig extends Config( new WithNDuplicatedRocketCores(8) ++ new FireSimRocketChipSingleCoreConfig) +// SHA-3 accelerator config +class FireSimRocketChipSha3L2Config extends Config( + new WithInclusiveCache ++ + new sha3.WithSha3Accel ++ + new WithNBigCores(1) ++ + new FireSimRocketChipConfig) + class FireSimBoomConfig extends Config( new WithBootROM ++ new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ From fcd48ad262532b2b782b72e33a4836f00f43a73f Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Thu, 3 Oct 2019 19:36:00 -0700 Subject: [PATCH 11/37] fix power straps --- .gitmodules | 6 +++--- vlsi/example-vlsi | 14 ++++++++++---- vlsi/example.yml | 4 ++++ vlsi/hammer | 2 +- 4 files changed, 18 insertions(+), 8 deletions(-) diff --git a/.gitmodules b/.gitmodules index 35addf76..901df05f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -60,10 +60,10 @@ url = https://github.com/freechipsproject/firrtl-interpreter.git [submodule "vlsi/hammer-cadence-plugins"] path = vlsi/hammer-cadence-plugins - url = git@github.com:ucb-bar/hammer-cadence-plugins.git + url = https://github.com/ucb-bar/hammer-cadence-plugins.git [submodule "vlsi/hammer-synopsys-plugins"] path = vlsi/hammer-synopsys-plugins - url = git@github.com:ucb-bar/hammer-synopsys-plugins.git + url = https://github.com/ucb-bar/hammer-synopsys-plugins.git [submodule "vlsi/hammer-mentor-plugins"] path = vlsi/hammer-mentor-plugins - url = git@github.com:ucb-bar/hammer-mentor-plugins.git + url = https://github.com/ucb-bar/hammer-mentor-plugins.git diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index 516ef588..21ff9598 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -24,7 +24,7 @@ def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: x.append(''' # TODO # Place custom TCL here -set_db route_design_bottom_routing_layer 2 +set_db route_design_bottom_routing_layer 1 set_db route_design_top_routing_layer 7 ''') return True @@ -32,6 +32,7 @@ set_db route_design_top_routing_layer 7 def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool: """ Scale the final GDS by a factor of 4 + hammer/src/hammer-vlsi/technology/asap7/__init__.py implements scale_gds_script """ x.append(''' # Write script out to a temporary file and execute it @@ -53,16 +54,21 @@ class ExampleDriver(CLIDriver): # Default set of steps can be found in the CAD tool plugin's __init__.py # make_pre_insertion_hook will execute the custom hook before the specified step - hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), # SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK) + # SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK) + # hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), + # make_post_insertion_hook will execute the custom hook after the specified step hammer_vlsi.HammerTool.make_post_insertion_hook("init_design", example_tool_settings), + # make_replacement_hook will replace the specified step with a custom hook - hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells), + # hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells), + # make_removal_hook will remove the specified step from the flow hammer_vlsi.HammerTool.make_removal_hook("place_bumps"), + # The target step in any of the above calls may be a default step or another one of your custom hooks - # This is an example of a technology-supplied hook (look in hammer/src/hammer-vlsi/technology/asap7/__init__.py) + # This is an example of a technology-supplied hook hammer_vlsi.HammerTool.make_post_insertion_hook("write_design", scale_final_gds) ] return extra_hooks diff --git a/vlsi/example.yml b/vlsi/example.yml index 3f8c0f23..32dc23d3 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -34,7 +34,11 @@ par.generate_power_straps_options: - M7 - M8 - M9 + pin_layers: + - M9 track_width: 5 + track_width_M2: 7 # minimum allowed + track_width_M3: 7 # minimum allowed track_spacing: 0 track_start: 10 power_utilization: 0.05 diff --git a/vlsi/hammer b/vlsi/hammer index b5024772..e30da8cc 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit b50247729bc536522ae42e8adb5e38277095775b +Subproject commit e30da8cc55297db0d6fe28cfe3309f77450944c0 From ff9f54525d0c9887433130840b0f12cd371896e0 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Thu, 3 Oct 2019 21:35:05 -0700 Subject: [PATCH 12/37] turns out you need to place a 1 core site tall obstruction or else V1's will short from power straps --- vlsi/example.yml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/vlsi/example.yml b/vlsi/example.yml index 32dc23d3..024e844f 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -36,9 +36,7 @@ par.generate_power_straps_options: - M9 pin_layers: - M9 - track_width: 5 - track_width_M2: 7 # minimum allowed - track_width_M3: 7 # minimum allowed + track_width: 7 # minimum allowed for M2 & M3 track_spacing: 0 track_start: 10 power_utilization: 0.05 @@ -58,7 +56,7 @@ vlsi.inputs.placement_constraints: left: 0 right: 0 top: 0 - bottom: 1.08 #must be at least this number + bottom: 0 - path: "Sha3AccelwBB/dco" type: hardmacro x: 108 @@ -67,6 +65,13 @@ vlsi.inputs.placement_constraints: height: 128 orientation: r0 top_layer: M9 + - path: "Sha3AccelwBB/place_obs_bottom" + type: obstruction + obs_types: ["place"] + x: 0 + y: 0 + width: 300 + height: 1.08 # 1 core site tall, necessary to avoid shorts # Pin placement constraints vlsi.inputs.pin_mode: generated From 9fa76f61417d757e35dc85f6470e957ad1f01e2c Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Fri, 4 Oct 2019 00:27:44 -0700 Subject: [PATCH 13/37] post-par sim, align dco straps --- vlsi/example-vlsi | 2 +- vlsi/extra_libraries/example/ExampleDCO.gds | Bin 8556 -> 8556 bytes vlsi/extra_libraries/example/ExampleDCO.lef | 108 ++++++++++---------- vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- 5 files changed, 56 insertions(+), 58 deletions(-) diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index 21ff9598..f853a1ed 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -24,7 +24,7 @@ def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: x.append(''' # TODO # Place custom TCL here -set_db route_design_bottom_routing_layer 1 +set_db route_design_bottom_routing_layer 2 set_db route_design_top_routing_layer 7 ''') return True diff --git a/vlsi/extra_libraries/example/ExampleDCO.gds b/vlsi/extra_libraries/example/ExampleDCO.gds index 556f117ced6baa701af624cb5670c1bafdc0e7fe..4864e115aa2875efd1cc3ceb0dbabe47dda18668 100644 GIT binary patch literal 8556 zcmbuEUuf1<7{{OY_4T(gr_MC<1(O-{2aBA}(!q*ZQz$_rB}J1>x3^lo_Ks;O81xGa zGBElB1{o++Xi$+|b@^UJmtA)g{kiI@`)+!kbN0#O&(ra=9XNjGch8s4&h|U=63=o8Vo;{74>4*nPVqr+pX~@_sNrUNven_rN`kA8#$)o+izs}i3nx*$ca%Ixb96d-L?Fat#>b12&x1Ar7E0cca=t1&m zKk#pKc9DBZ?}y~dq@Ou@kUZKC{P(KY*8RHe{E%Fk^fN~fl1KZ2f0MI|JXm@^Bv&T= z%+Z77(SG26SiQD}bldqMxiaZzjvgeB_5=U0vx{siy&sY*lYZvtLGoxn@NZYItr6XJ zen_rN`kA8#$)o+iKkDovkComJ$(2bzbMzp2v>*7#)NAVr-FALRu1xxwqX)^O{lLG= z*+q7j-Ve!@Nk4P+AbGSO_@7d*tv$N!{E%Fk^fN~fl1KZ2f3LHP>?^$=k}H#b=IBB4 zXg}~jt6p0NbldqMxiaZzjvgeB_5=SxXBRnCdOsvrCjHFOgXGbE;6I{XTSs-<`60P7 z>1U1}B#-t3|D?%v9V@*bPFkpI@;2w!&$~qrk}Gfh`UC%TDQ>->f7Qth0-}QF=clS0??;(SzjCe&Byo zy|&)cZRdyN%A}t;dXPNY5B%qxUF7Z3`ysh9>1U1}B#-t3|2yin^{#F^KO|Qs{mjvW z*6CP_M0zbldqMxiaZzjvgeB_5=S#XBYXn^nOUL zO!}Fl2g#%T!2gMQZGEcS&JW3zNk4P+AbGSO_%A!V$d%IjA-OW?XO12ukM;xqXX>@} zg>E}PBv&T=%+Z77(SG2+=IkP0mfjD^l}SHy^dNb(ANapgudQ!%+xa26GU;cI9wd+U z1OIhr7x}LAen_rN`kA8#$)kPmul+JB_Wqya68-RxLHGWjBf0Xw{0r%C4c~uU_LJ0p z?ur=yoD^9(bc5u|(C_>6ufG=Dpa1?BUGF!Vzi;pc&2M?iKmU0*m)T$K&foCwpW5?g zOKBeaenN8h=~X(?>)*d!v&jC2MfUys#|!`Z{m*aV{n15!{ks?0e`b;W!wc>A|NH*^ z+PXdz#a%U7D*g5@zWy(Q)W@W+SxnEIdZ{(%?@M~V=*mE|nCqOLIN54X96vI2G^e#} z?B>>%tk%kkYim|(O~o~w)mm3^ZOdxiU2#2<)!JBbJ(|_Juj1OC)!I~X?Z|3vuDC|B zTEktrBYZZt=);lobnF5W!>`hev0c2<4*h~)HkRek!9Fsqt zyQxn5f8DkH?q_$Sm3P+;R$O^^?fHr;@2*W&TzPk`RdMCrwV8@5@2^J74u>-n9!|S=%h8I@7I*xz>xXwU3?Z z%-KISIrrwnu}C-boEKx>%(GsKc{9&@Ip)p${qlLtoB2EDTFk4LBXZa@wCK&WjL+77T!D7}FN>FK%qRFP)TUoQov=j_Ffk6g_ z6&PgTpdy2c?5fLMb=`HBb=OsNSvP%u@7c#4ACG5e+YcT;_I-a}KJVF{$6j7nxn}dQ zTis}O{^{;sG{ncT1Yp?(@e_ogQuVKfm8CU$F4mU6;1){q@_wcl7_VapKyM zgKqW0OuLHP9gCc+?rXZoUA3g?oO^QV0{y9J_%@vVXZM7=MRKv@e&=rQ|2NNm zb^73k_`5^^4fIivhzc7G3#fK9wblpBY(HaHA{W)Lvk_eXOA8vPxd4K zGI?!Q=(6)eaxv>?j~*mX_9Oo)lWTf>@I!Jj>t~N1Bv1Au|7v+{*66bHLvk_eXOA8v zPxd4KT9a!Y_Q4Oy#jKw_dXPNXkNl6wYx9^cJ3k~BvwrsILGolj@~<KO`5ke)i}=@?<~q_sMJXoGv>*Bp0)O_UJ+KWIyunHo0bx z4}M54X8r8ZgXGD6xazt7~F{XY01xtR5{M-P%G`;q@8 zd2J5rvhzc7G3#fK9wblpBmW_jYYzM1hvZ_`&mKKUp6o~dqw?Au(`Dy}_`3~d2NpS;DPh7W#7F5cOXK7X@E50WSQ(fLowYcr86{p`_$Ie@|YU_jTF% zA-S0Kvquk-C;O5AqRBNM_~3`+V%Eaz1gaxv>?j~*mX_9OpwlWQh?@I!Jj>t~N1Bv1Au|5x(be51?G56Q)>pFMhz zJlT)@H%zYi&Idmv7qfo$=t1&iKk|Psug#CT?EH{i%=+1*2g#HD$bZx1nxB2}Lvk_e zXOA8vPxgbq@z+rM`@c39=&%3keZYoyynZ)7ug|8xIsX3fiPNs}`=oP5doSw`Op{!U z{h>eg`Df1ksh|IbpMu|L{@yFoH2>7=clFPqzpQ=!j`01d-ETIc{T%E)KyqX3Up~+N zntAra_s4U8|KayH_x{d#zW+V*>>rqC|HxeXUAMl!U)j_>Q9amj3tg9ei{JU1bIm@t zxThL9dG__zc(`Bk`_-gd+Ea~>of|yU8XY`wwD(v^>)yWGTbqhn-8I+dqSo@7YfDjU zRn4`vsP$0I^;A)7ZO!#`QR~r~YgNhQ~%)gX68&-X1-Ec5K}KXH)XreA<`j7M}BJ z%3FBWYbkHxd9SCuh5x>Mo$?m`8*?M&)k9M9bN(Ua)uU3 Date: Thu, 3 Oct 2019 01:52:36 +0000 Subject: [PATCH 14/37] [firechip] Remove SimConfigs --- .../firechip/src/main/scala/SimConfigs.scala | 42 ------------------- 1 file changed, 42 deletions(-) delete mode 100644 generators/firechip/src/main/scala/SimConfigs.scala diff --git a/generators/firechip/src/main/scala/SimConfigs.scala b/generators/firechip/src/main/scala/SimConfigs.scala deleted file mode 100644 index 06e6aa93..00000000 --- a/generators/firechip/src/main/scala/SimConfigs.scala +++ /dev/null @@ -1,42 +0,0 @@ -//See LICENSE for license details. -package firesim.firesim - -import freechips.rocketchip.config.{Parameters, Config, Field} - -import midas.models._ - -import firesim.endpoints._ -import firesim.configs._ - -/******************************************************************************* -* Full PLATFORM_CONFIG Configurations. These set simulator parameters. -* -* In general, if you're adding or removing features from any of these, you -* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager -* will store this name as part of the tags for the AGFI, so that later you can -* reconstruct what is in a particular AGFI. These tags are also used to -* determine which driver to build. -*******************************************************************************/ -class FireSimConfig extends Config(new BasePlatformConfig) - -class FireSimClockDivConfig extends Config( - new FireSimConfig) - -class FireSimDDR3Config extends Config( - new FireSimConfig) - -class FireSimDDR3LLC4MBConfig extends Config( - new FireSimConfig) - -class FireSimDDR3FRFCFSConfig extends Config( - new FireSimConfig) - -class FireSimDDR3FRFCFSLLC4MBConfig extends Config( - new FireSimConfig) - -class FireSimDDR3FRFCFSLLC4MB3ClockDivConfig extends Config( - new FireSimConfig) - -class Midas2Config extends Config( - new WithMultiCycleRamModels ++ - new FireSimConfig) From 5845862525d69cf14db1c9fb634ed335962bb4c7 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 3 Oct 2019 02:28:48 +0000 Subject: [PATCH 15/37] [Firechip] Push FASED configs into TargetConfigs.scala --- generators/firechip/src/main/scala/TargetConfigs.scala | 7 ++++++- .../firechip/src/test/scala/ScalaTestSuite.scala | 10 +++++----- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index d88ffa25..d0c55ed3 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -20,7 +20,7 @@ import icenet._ import firesim.endpoints._ import firesim.util.{WithNumNodes} -import firesim.configs.WithDefaultMemModel +import firesim.configs._ class WithBootROM extends Config((site, here, up) => { case BootROMParams => { @@ -86,6 +86,11 @@ class WithScalaTestFeatures extends Config((site, here, up) => { case PrintTracePort => true }) +// FASED Config Aliases. This to enable config generation via "_" concatenation +// which requires that all config classes be defined in the same package +class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB +class DDR3FRFCFSLLC4MB3Div extends FRFCFS16GBQuadRankLLC4MB3Div + /******************************************************************************* * Full TARGET_CONFIG configurations. These set parameters of the target being * simulated. diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 77415636..49737be4 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -130,10 +130,10 @@ abstract class FireSimTestSuite( runSuite("verilator")(FastBlockdevTests) } -class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimConfig") -class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "FireSimConfig") -class RocketNICF1Tests extends FireSimTestSuite("FireSim", "FireSimRocketChipConfig", "FireSimConfig") { +class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipQuadCoreConfig_DDR3FRFCFSLLC4MB", "BaseF1Config") +class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig_DDR3FRFCFSLLC4MB", "BaseF1Config") +class RocketNICF1Tests extends FireSimTestSuite("FireSim", "FireSimRocketChipConfig_DDR3FRFCFSLLC4MB", "BaseF1Config") { runSuite("verilator")(NICLoopbackTests) } -class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "Midas2Config") -class RamModelBoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "Midas2Config") +class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams") +class RamModelBoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "BaseF1Config_MCRams") From 7c0bb51242e1a9915c16934edfbdd886537c9fb1 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 4 Oct 2019 18:15:34 +0000 Subject: [PATCH 16/37] [firechip] Update scalatest suite --- generators/firechip/src/test/scala/ScalaTestSuite.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 49737be4..e7194d8c 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -130,9 +130,9 @@ abstract class FireSimTestSuite( runSuite("verilator")(FastBlockdevTests) } -class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipQuadCoreConfig_DDR3FRFCFSLLC4MB", "BaseF1Config") -class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig_DDR3FRFCFSLLC4MB", "BaseF1Config") -class RocketNICF1Tests extends FireSimTestSuite("FireSim", "FireSimRocketChipConfig_DDR3FRFCFSLLC4MB", "BaseF1Config") { +class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig", "BaseF1Config") +class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config") +class RocketNICF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimRocketChipConfig", "BaseF1Config") { runSuite("verilator")(NICLoopbackTests) } class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams") From 39172e0d385f40763bbff217a1d99351c0b14240 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 4 Oct 2019 18:27:19 +0000 Subject: [PATCH 17/37] [CI] Update FireSim defaults --- .circleci/defaults.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 8497f304..f5387bd8 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -47,6 +47,6 @@ mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig" mapping["rocketchip"]="SUB_PROJECT=rocketchip" mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketConfig TOP=TopWithBlockDevice" mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaRocketConfig GENERATOR_PACKAGE=hwacha" -mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=FireSimRocketChipConfig PLATFORM_CONFIG=FireSimConfig" -mapping["fireboom"]="DESIGN=FireBoom TARGET_CONFIG=FireSimBoomConfig PLATFORM_CONFIG=FireSimConfig" -mapping["firesim-clockdiv"]="DESIGN=FireSim TARGET_CONFIG=FireSimRocketChipConfig PLATFORM_CONFIG=FireSimClockDivConfig" +mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=FireSimConfig" +mapping["fireboom"]="DESIGN=FireBoom TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=FireSimConfig" +mapping["firesim-clockdiv"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB3Div_FireSimRocketChipConfig PLATFORM_CONFIG=FireSimClockDivConfig" From 6210ca2df870fc13f147bf417dc4525b72b254fc Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 4 Oct 2019 21:03:16 +0000 Subject: [PATCH 18/37] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 26ffba7c..4c1a3aa2 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 26ffba7cbca2982fef6b221a7abbc51d5cdc4b62 +Subproject commit 4c1a3aa2122d35c505e8135642bfb6870f2fce19 From 36b269bfc9aa8582150abb5011f1c5e60a7e00e2 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 4 Oct 2019 21:51:39 +0000 Subject: [PATCH 19/37] [CI] Fix PLATFORM_CONFIG in firesim --- .circleci/defaults.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index f5387bd8..bdc53e80 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -47,6 +47,6 @@ mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig" mapping["rocketchip"]="SUB_PROJECT=rocketchip" mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketConfig TOP=TopWithBlockDevice" mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaRocketConfig GENERATOR_PACKAGE=hwacha" -mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=FireSimConfig" -mapping["fireboom"]="DESIGN=FireBoom TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=FireSimConfig" -mapping["firesim-clockdiv"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB3Div_FireSimRocketChipConfig PLATFORM_CONFIG=FireSimClockDivConfig" +mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config" +mapping["fireboom"]="DESIGN=FireBoom TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=BaseF1Config" +mapping["firesim-clockdiv"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB3Div_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config" From 53f58f6baa21f2cf2c818f0cdbea8004f181d23e Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 25 Sep 2019 15:41:21 -0700 Subject: [PATCH 20/37] Support serializable endpoints; Golden Gate stage --- build.sbt | 1 + .../firechip/src/main/scala/EndpointBinders.scala | 10 +++------- generators/firechip/src/main/scala/Generator.scala | 9 +++++---- .../firechip/src/test/scala/ScalaTestSuite.scala | 5 +++-- sims/firesim | 2 +- vlsi/hammer | 2 +- 6 files changed, 14 insertions(+), 15 deletions(-) diff --git a/build.sbt b/build.sbt index 4d747829..ccc9e87f 100644 --- a/build.sbt +++ b/build.sbt @@ -23,6 +23,7 @@ lazy val commonSettings = Seq( addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"), + exportJars := true, resolvers ++= Seq( Resolver.sonatypeRepo("snapshots"), Resolver.sonatypeRepo("releases"), diff --git a/generators/firechip/src/main/scala/EndpointBinders.scala b/generators/firechip/src/main/scala/EndpointBinders.scala index 0450f8f3..cc76503d 100644 --- a/generators/firechip/src/main/scala/EndpointBinders.scala +++ b/generators/firechip/src/main/scala/EndpointBinders.scala @@ -14,8 +14,7 @@ import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp import icenet.HasPeripheryIceNICModuleImpValidOnly import junctions.{NastiKey, NastiParameters} -import midas.widgets.{IsEndpoint} -import midas.models.{FASEDEndpoint, FasedAXI4Edge} +import midas.models.{FASEDEndpoint, AXI4EdgeSummary, CompleteConfig} import firesim.endpoints._ import firesim.configs.MemModelKey import firesim.util.RegisterEndpointBinder @@ -55,11 +54,8 @@ class WithFASEDEndpoint extends RegisterEndpointBinder({ val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, axi4Bundle.ar.bits.addr.getWidth, axi4Bundle.ar.bits.id.getWidth) - val fasedP = p.alterPartial({ - case NastiKey => nastiKey - case FasedAXI4Edge => Some(edge) - }) - FASEDEndpoint(axi4Bundle, t.reset.toBool, p(MemModelKey)(fasedP))(fasedP) + FASEDEndpoint(axi4Bundle, t.reset.toBool, + CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)))) }) }).toSeq }) diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala index 169cbe1f..0c5b4909 100644 --- a/generators/firechip/src/main/scala/Generator.scala +++ b/generators/firechip/src/main/scala/Generator.scala @@ -2,7 +2,7 @@ package firesim.firesim -import java.io.{File} +import java.io.{File, FileWriter} import chisel3.experimental.RawModule import chisel3.internal.firrtl.{Circuit, Port} @@ -48,13 +48,14 @@ trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSu } object FireSimGenerator extends App with IsFireSimGeneratorLike { + val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs lazy val generatorArgs = GeneratorArgs(args) lazy val genDir = new File(names.targetDir) - elaborateAndCompileWithMidas + // The only reason this is not generateFirrtl; generateAnno is that we need to use a different + // JsonProtocol to properly write out the annotations. Fix once the generated are unified + elaborate generateTestSuiteMakefrags - generateHostVerilogHeader generateArtefacts - generateTclEnvFile } // For now, provide a separate generator app when not specifically building for FireSim diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index e7194d8c..0cda4b93 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -23,6 +23,8 @@ abstract class FireSimTestSuite( import scala.concurrent.duration._ import ExecutionContext.Implicits.global + val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs + lazy val generatorArgs = GeneratorArgs( midasFlowKind = "midas", targetDir = "generated-src", @@ -42,7 +44,6 @@ abstract class FireSimTestSuite( val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}", s"TARGET_CONFIG=${generatorArgs.targetConfigs}", s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}") - override lazy val platform = hostParams(midas.Platform) def invokeMlSimulator(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = { make((Seq(s"${outDir.getAbsolutePath}/${name}.%s".format(if (debug) "vpd" else "out"), @@ -122,7 +123,7 @@ abstract class FireSimTestSuite( clean mkdirs - elaborateAndCompileWithMidas + elaborate generateTestSuiteMakefrags runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-test-output0""")) diffTracelog("rv64ui-p-simple.out") diff --git a/sims/firesim b/sims/firesim index 4c1a3aa2..a94bea1d 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4c1a3aa2122d35c505e8135642bfb6870f2fce19 +Subproject commit a94bea1d16e858c4b04d03306fb100962b09dc9a diff --git a/vlsi/hammer b/vlsi/hammer index 1b07b9a3..a27886fb 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 1b07b9a378c2936389b95f7ee1436e1f492d55e2 +Subproject commit a27886fb42c121f3ba5f684acaf5856b2ec293e1 From 95a44ff6d06186d0bdaa72cb308b0bc37be76d93 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Fri, 4 Oct 2019 17:54:33 -0400 Subject: [PATCH 21/37] Switch to bash optarg for cli handling in init-submodules script --- scripts/init-submodules-no-riscv-tools.sh | 24 +++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index da34adf0..34b9ed8d 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -6,17 +6,24 @@ set -o pipefail RDIR=$(git rev-parse --show-toplevel) -NO_FIRESIM=false +_usage() { + echo "usage: ${0} [--no-firesim]" >&2 + exit 1 +} -while test $# -gt 0 -do - case "$1" in - --no-firesim) - NO_FIRESIM=true; - ;; +NO_FIRESIM=false +while getopts 'h-:' opt ; do + case ${opt} in + -) + case ${OPTARG} in + no-firesim) NO_FIRESIM=true ;; + *) echo "invalid option: --${OPTARG}" >&2 ; _usage ;; + esac ;; + h) _usage ;; + *) echo "invalid option: -${opt}" >&2 ; _usage ;; esac - shift done +shift $((OPTIND - 1)) # Ignore toolchain submodules cd "$RDIR" @@ -39,6 +46,7 @@ git config --unset submodule.vlsi/hammer-synopsys-plugins.update git config --unset submodule.vlsi/hammer-mentor-plugins.update if [ $NO_FIRESIM = false ]; then +echo "initializing firesim" # Renable firesim and init only the required submodules to provide # all required scala deps, without doing a full build-setup git config --unset submodule.sims/firesim.update From 8e8ce09ce92e239920732ee2352ef24f43074436 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Fri, 4 Oct 2019 19:04:08 -0400 Subject: [PATCH 22/37] Move qemu to chipyard from firesim --- .gitmodules | 3 +++ scripts/build-toolchains.sh | 3 +++ scripts/init-submodules-no-riscv-tools.sh | 2 ++ sims/firesim | 2 +- toolchains/qemu | 1 + 5 files changed, 10 insertions(+), 1 deletion(-) create mode 160000 toolchains/qemu diff --git a/.gitmodules b/.gitmodules index 4c23765e..2f4d9eb3 100644 --- a/.gitmodules +++ b/.gitmodules @@ -92,3 +92,6 @@ [submodule "vlsi/hammer-mentor-plugins"] path = vlsi/hammer-mentor-plugins url = git@github.com:ucb-bar/hammer-mentor-plugins.git +[submodule "toolchains/qemu"] + path = toolchains/qemu + url = https://github.com/qemu/qemu.git diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 738b5ae7..cde56227 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -121,6 +121,9 @@ cp -p "${SRCDIR}/riscv-isa-sim/build/libfesvr.a" "${RISCV}/lib/" CC= CXX= module_all riscv-pk --prefix="${RISCV}" --host=riscv64-unknown-elf module_all riscv-tests --prefix="${RISCV}/riscv64-unknown-elf" +# Common tools (not in any particular toolchain dir) +SRCDIR="$RDIR/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu + cd "$RDIR" { diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 34b9ed8d..8f90f2d1 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -30,6 +30,8 @@ cd "$RDIR" for name in toolchains/*/*/ ; do git config submodule."${name%/}".update none done +git config submodule.toolchains.qemu.update none + # Disable updates to the FireSim submodule until explicitly requested git config submodule.sims/firesim.update none # Disable updates to the hammer tool plugins repos diff --git a/sims/firesim b/sims/firesim index ffe68ac7..1e7f304c 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit ffe68ac7f69795b2cccf7d9510facd5e2db4edc6 +Subproject commit 1e7f304c49507b46cf77ccf5d21a807db633f35c diff --git a/toolchains/qemu b/toolchains/qemu new file mode 160000 index 00000000..4f591025 --- /dev/null +++ b/toolchains/qemu @@ -0,0 +1 @@ +Subproject commit 4f59102571fce49af180cfc6d4cdd2b5df7bdb14 From 3e2fba51505f470735adb11c4d8552ba1fd4dcd3 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Fri, 4 Oct 2019 19:06:47 -0400 Subject: [PATCH 23/37] Update firesim to a version that has this chipyard submoduled. --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 1e7f304c..3840b6e7 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 1e7f304c49507b46cf77ccf5d21a807db633f35c +Subproject commit 3840b6e7bfab7ad954d9494cf732cf99e0d86dc2 From f040db83c967d8f7f494d83dffc85705ac372b96 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Fri, 4 Oct 2019 16:38:59 -0700 Subject: [PATCH 24/37] toolchains: Bump esp-isa-sim This fixes the libhwacha.so build. --- toolchains/esp-tools/riscv-isa-sim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim index 92f2f467..0ffa02e5 160000 --- a/toolchains/esp-tools/riscv-isa-sim +++ b/toolchains/esp-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 92f2f467c00caa991379ba55ece7118f068c2218 +Subproject commit 0ffa02e5b4ca57ec44684119a1a9a31b3871857b From 151d3f16c3260a00e427372b9dd866e32d9b9e68 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Sat, 5 Oct 2019 00:24:31 +0000 Subject: [PATCH 25/37] typo in command for ignoring qemu submodule --- scripts/init-submodules-no-riscv-tools.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 8f90f2d1..0ce30475 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -30,7 +30,7 @@ cd "$RDIR" for name in toolchains/*/*/ ; do git config submodule."${name%/}".update none done -git config submodule.toolchains.qemu.update none +git config submodule.toolchains/qemu.update none # Disable updates to the FireSim submodule until explicitly requested git config submodule.sims/firesim.update none @@ -43,6 +43,8 @@ git submodule update --init --recursive #--jobs 8 for name in toolchains/*/*/ ; do git config --unset submodule."${name%/}".update done +git config --unset submodule.toolchains/qemu.update + git config --unset submodule.vlsi/hammer-cadence-plugins.update git config --unset submodule.vlsi/hammer-synopsys-plugins.update git config --unset submodule.vlsi/hammer-mentor-plugins.update From ad76e0ad1c735862e49f3009d54f82f006721e71 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 3 Oct 2019 15:56:05 -0700 Subject: [PATCH 26/37] Bump FireSim; Revert an errant hammer bump --- sims/firesim | 2 +- vlsi/hammer | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sims/firesim b/sims/firesim index a94bea1d..9bd6679e 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit a94bea1d16e858c4b04d03306fb100962b09dc9a +Subproject commit 9bd6679ea8d3f7d3e99e827d1cd27322d7b498b1 diff --git a/vlsi/hammer b/vlsi/hammer index a27886fb..1b07b9a3 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit a27886fb42c121f3ba5f684acaf5856b2ec293e1 +Subproject commit 1b07b9a378c2936389b95f7ee1436e1f492d55e2 From 370c0dbfa88ce8e79c9c61cf41911d06580c3ac2 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 5 Oct 2019 21:16:31 +0000 Subject: [PATCH 27/37] Bump FireSim [ci skip] --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 4c1a3aa2..31682ca9 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4c1a3aa2122d35c505e8135642bfb6870f2fce19 +Subproject commit 31682ca9957ea20a823ab313285b1a95a6dfeb80 From aa6e09f80056852e52a4a9d21161f558ebeb90f8 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 6 Oct 2019 03:32:50 +0000 Subject: [PATCH 28/37] Rename Endpoint -> Bridge --- .../FPGA-Accelerated-Simulators.rst | 2 +- ...pointBinders.scala => BridgeBinders.scala} | 48 +++++++++---------- .../src/main/scala/TargetConfigs.scala | 6 +-- .../src/main/scala/TargetMixins.scala | 4 +- 4 files changed, 30 insertions(+), 30 deletions(-) rename generators/firechip/src/main/scala/{EndpointBinders.scala => BridgeBinders.scala} (52%) diff --git a/docs/Simulation/FPGA-Accelerated-Simulators.rst b/docs/Simulation/FPGA-Accelerated-Simulators.rst index 29f42880..c8640f9d 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulators.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulators.rst @@ -87,4 +87,4 @@ will look as follows: You should then be able to refer to those classes or an alias of them in your ``DESIGN`` or ``TARGET_CONFIG`` variables. Note that if your target machine has I/O not provided in the default FireChip targets (see ``generators/firechip/src/main/scala/Targets.scala``) you may need -to write a custom endpoint. +to write a custom bridge. diff --git a/generators/firechip/src/main/scala/EndpointBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala similarity index 52% rename from generators/firechip/src/main/scala/EndpointBinders.scala rename to generators/firechip/src/main/scala/BridgeBinders.scala index cc76503d..c2bed0e5 100644 --- a/generators/firechip/src/main/scala/EndpointBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -14,12 +14,12 @@ import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp import icenet.HasPeripheryIceNICModuleImpValidOnly import junctions.{NastiKey, NastiParameters} -import midas.models.{FASEDEndpoint, AXI4EdgeSummary, CompleteConfig} -import firesim.endpoints._ +import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig} +import firesim.bridges._ import firesim.configs.MemModelKey -import firesim.util.RegisterEndpointBinder +import firesim.util.RegisterBridgeBinder -class WithTiedOffDebug extends RegisterEndpointBinder({ case target: HasPeripheryDebugModuleImp => +class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp => target.debug.clockeddmi.foreach({ cdmi => cdmi.dmi.req.valid := false.B cdmi.dmi.req.bits := DontCare @@ -30,23 +30,23 @@ class WithTiedOffDebug extends RegisterEndpointBinder({ case target: HasPeripher Seq() }) -class WithSerialEndpoint extends RegisterEndpointBinder({ - case target: HasPeripherySerialModuleImp => Seq(SerialEndpoint(target.serial)(target.p)) +class WithSerialBridge extends RegisterBridgeBinder({ + case target: HasPeripherySerialModuleImp => Seq(SerialBridge(target.serial)(target.p)) }) -class WithNICEndpoint extends RegisterEndpointBinder({ - case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICEndpoint(target.net)(target.p)) +class WithNICBridge extends RegisterBridgeBinder({ + case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.net)(target.p)) }) -class WithUARTEndpoint extends RegisterEndpointBinder({ - case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTEndpoint(u)(target.p)) +class WithUARTBridge extends RegisterBridgeBinder({ + case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(u)(target.p)) }) -class WithBlockDeviceEndpoint extends RegisterEndpointBinder({ - case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(target.bdev, target.reset.toBool)(target.p)) +class WithBlockDeviceBridge extends RegisterBridgeBinder({ + case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.bdev, target.reset.toBool)(target.p)) }) -class WithFASEDEndpoint extends RegisterEndpointBinder({ +class WithFASEDBridge extends RegisterBridgeBinder({ case t: CanHaveMasterAXI4MemPortModuleImp => implicit val p = t.p (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => @@ -54,23 +54,23 @@ class WithFASEDEndpoint extends RegisterEndpointBinder({ val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, axi4Bundle.ar.bits.addr.getWidth, axi4Bundle.ar.bits.id.getWidth) - FASEDEndpoint(axi4Bundle, t.reset.toBool, + FASEDBridge(axi4Bundle, t.reset.toBool, CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)))) }) }).toSeq }) -class WithTracerVEndpoint extends RegisterEndpointBinder({ - case target: HasTraceIOImp => TracerVEndpoint(target.traceIO)(target.p) +class WithTracerVBridge extends RegisterBridgeBinder({ + case target: HasTraceIOImp => TracerVBridge(target.traceIO)(target.p) }) -// Shorthand to register all of the provided endpoints above -class WithDefaultFireSimEndpoints extends Config( +// Shorthand to register all of the provided bridges above +class WithDefaultFireSimBridges extends Config( new WithTiedOffDebug ++ - new WithSerialEndpoint ++ - new WithNICEndpoint ++ - new WithUARTEndpoint ++ - new WithBlockDeviceEndpoint ++ - new WithFASEDEndpoint ++ - new WithTracerVEndpoint + new WithSerialBridge ++ + new WithNICBridge ++ + new WithUARTBridge ++ + new WithBlockDeviceBridge ++ + new WithFASEDBridge ++ + new WithTracerVBridge ) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index d0c55ed3..689927b0 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -18,7 +18,7 @@ import scala.math.{min, max} import tracegen.TraceGenKey import icenet._ -import firesim.endpoints._ +import firesim.bridges._ import firesim.util.{WithNumNodes} import firesim.configs._ @@ -113,7 +113,7 @@ class FireSimRocketChipConfig extends Config( new WithPerfCounters ++ new WithoutClockGating ++ new WithDefaultMemModel ++ - new WithDefaultFireSimEndpoints ++ + new WithDefaultFireSimBridges ++ new freechips.rocketchip.system.DefaultConfig) class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => { @@ -163,7 +163,7 @@ class FireSimBoomConfig extends Config( new WithDefaultMemModel ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ - new WithDefaultFireSimEndpoints ++ + new WithDefaultFireSimBridges ++ new freechips.rocketchip.system.BaseConfig ) diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 0c7d2eb9..43d03853 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -11,12 +11,12 @@ import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.util._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.rocket.TracedInstruction -import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction} +import firesim.bridges.{TraceOutputTop, DeclockedTracedInstruction} import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation} /* Wires out tile trace ports to the top; and wraps them in a Bundle that the - * TracerV endpoint can match on. + * TracerV bridge can match on. */ object PrintTracePort extends Field[Boolean](false) From 115102c987f9400bead34d99808ffcbb9050c91d Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 6 Oct 2019 03:36:12 +0000 Subject: [PATCH 29/37] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 9bd6679e..a1f3a927 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 9bd6679ea8d3f7d3e99e827d1cd27322d7b498b1 +Subproject commit a1f3a927a975dea1200a56260c140998866a1c51 From 577cede749089b0290e6e6bd31f9b491e4b293cd Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Sat, 5 Oct 2019 01:08:59 -0700 Subject: [PATCH 30/37] sha3: Bump for RTL fixes/optimizations --- generators/sha3 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sha3 b/generators/sha3 index b364cd36..e6f5bab6 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit b364cd367ceb8636b8dbec3c46bf1aab1788b2c3 +Subproject commit e6f5bab675bfdad0ebdc23239adbd52ca89706e6 From 427082ba7096a9d9cc2ad90c96faeaa39bdfac01 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Sun, 6 Oct 2019 14:28:03 -0700 Subject: [PATCH 31/37] [skip ci] address John's comments --- docs/VLSI/Tutorial.rst | 6 +++--- vlsi/example.yml | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst index de6e0166..db1cee60 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/Tutorial.rst @@ -54,7 +54,7 @@ Prerequisites * Genus, Innovus, and Calibre licenses * For ASAP7 specifically: - * Download the `ASAP7 PDK `__ tarball to a directory of choice but do not extract it. The tech plugin will extract and setup the PDK for you into a cache directory. + * Download the `ASAP7 PDK `__ tarball to a directory of choice but do not extract it. The tech plugin is configured to extract the PDK into a cache directory for you. * If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision. They may live outside ``extra_libraries`` at your discretion. * Innovus version must be >= 15.2 or <= 18.1 (ISRs excluded). @@ -84,7 +84,7 @@ To elaborate the ``Sha3RocketConfig`` (Rocket Chip w/ the accelerator) and set u make buildfile MACROCOMPILER_MODE='--mode synflops' CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB -The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead. Note this will dramatically increase synthesis runtimes if your design has a lot of caches. +The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler, so flip-flop arrays are used instead. This will dramatically increase the synthesis runtime if your design has a lot of memory state (e.g. large caches). The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket Chip with the Sha3Accel module. @@ -99,7 +99,7 @@ example-vlsi ^^^^^^^^^^^^ This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. -The ``scale_final_gds`` hook is a particularly powerful hook. It dumps a Python script provided by the ASAP7 tech plugin, an executes it within the Innovus TCL interpreter. This hook is run after ``write_design`` because the ASAP7 PDK requires post-par GDSs to be scaled down by a factor of 4. +The ``scale_final_gds`` hook is a particularly powerful hook. It dumps a Python script provided by the ASAP7 tech plugin, an executes it within the Innovus TCL interpreter, and should be inserted after ``write_design``. This hook is necessary because the ASAP7 PDK does place-and-route using 4x upscaled LEFs for Innovus licensing reasons, thereby requiring the cells created in the post-P&R GDS to be scaled down by a factor of 4. example.yml ^^^^^^^^^^^ diff --git a/vlsi/example.yml b/vlsi/example.yml index 024e844f..c8e4a72b 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -38,6 +38,7 @@ par.generate_power_straps_options: - M9 track_width: 7 # minimum allowed for M2 & M3 track_spacing: 0 + track_spacing_M3: 1 # to avoid M2 shorts at higher density track_start: 10 power_utilization: 0.05 power_utilization_M8: 1.0 From e0b4f21ce6d907aed13076afc74e5ba5e4f3a107 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Sun, 6 Oct 2019 18:46:22 -0400 Subject: [PATCH 32/37] fixup circular reference with firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 6d578eeb..226df1d6 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 6d578eeb40b6da88e192d0ab4844b3ac690868f3 +Subproject commit 226df1d6134aca22e1e1592935b0b8033f8e0734 From 9f42db804cd15b7b54c3346562d2b6ab00f5043e Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 6 Oct 2019 22:49:35 +0000 Subject: [PATCH 33/37] [FireChip] Add an alias for L2 Config Mixins --- generators/firechip/src/main/scala/TargetConfigs.scala | 3 +++ 1 file changed, 3 insertions(+) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 689927b0..c91ae05e 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -91,6 +91,9 @@ class WithScalaTestFeatures extends Config((site, here, up) => { class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB class DDR3FRFCFSLLC4MB3Div extends FRFCFS16GBQuadRankLLC4MB3Div +// L2 Config Aliases. For use with "_" concatenation +class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache + /******************************************************************************* * Full TARGET_CONFIG configurations. These set parameters of the target being * simulated. From c7cba24bf608219328ff3a586c29a41fc43e976b Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Sun, 6 Oct 2019 19:13:40 -0400 Subject: [PATCH 34/37] Add qemu to CI rules for rebuilding toolchain --- .circleci/create-hash.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/create-hash.sh b/.circleci/create-hash.sh index 63dfa242..939eeb31 100755 --- a/.circleci/create-hash.sh +++ b/.circleci/create-hash.sh @@ -15,7 +15,7 @@ cd $LOCAL_CHIPYARD_DIR # Use normalized output of git-submodule status as hashfile for tools in 'riscv-tools' 'esp-tools' ; do - git submodule status "toolchains/${tools}" | while read -r line ; do + git submodule status "toolchains/${tools}" "toolchains/qemu" | while read -r line ; do echo "${line#[!0-9a-f]}" done > "${HOME}/${tools}.hash" done From 0d84e3646e339d5e4b07fdbbb89abb6a19a73329 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Sun, 6 Oct 2019 23:38:46 -0400 Subject: [PATCH 35/37] adds sha3 workload to firemarshal --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 226df1d6..22ce787f 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 226df1d6134aca22e1e1592935b0b8033f8e0734 +Subproject commit 22ce787fab2515c81bfbc98bbfdcd94b075d7a8a From 79f3776966460ebc5dd8a303458c5a26ad85b051 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Sun, 6 Oct 2019 22:57:13 -0700 Subject: [PATCH 36/37] add ability to view gds using gdspy --- docs/VLSI/Tutorial.rst | 8 +++++ vlsi/view_gds.py | 66 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) create mode 100755 vlsi/view_gds.py diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst index db1cee60..66a2f220 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/Tutorial.rst @@ -127,6 +127,14 @@ Intermediate database are written in ``build/par-rundir`` between each step of t Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files. +`gdspy` can be used to `view the final layout `__, but it is somewhat crude and slow (wait a few minutes for it to load): + +.. code-block:: shell + + ``python3 view_gds.py build/par-rundir/Sha3AccelwBB.gds`` + +By default, this script only shows the M2 thru M4 routing. Layers can be toggled in the layout viewer's side pane and ``view_gds.py`` has a mapping of layer numbers to layer names. + DRC & LVS ^^^^^^^^^ To run DRC & LVS, and view the results in Calibre: diff --git a/vlsi/view_gds.py b/vlsi/view_gds.py new file mode 100755 index 00000000..edc94926 --- /dev/null +++ b/vlsi/view_gds.py @@ -0,0 +1,66 @@ +import sys + +try: + import gdspy +except ImportError: + print('Bad gdspy installation!') + sys.exit() + +print('Loading GDS...') +gds_lib = gdspy.GdsLibrary().read_gds(infile=str(sys.argv[1]), units='import') + +# Comment to show layer +hidden=[ + (1, 0), #well + (1, 251), #well lbl + (2, 0), #fin + (3, 0), #psub + (3, 251), #psub lbl + (7, 0), #gate + (8, 0), #dummy + (10, 0), #gate cut + (11, 0), #active + (12, 0), #nselect + (13, 0), #pselect + (16, 0), #LIG + (17, 0), #LISD + (18, 0), #V0 + (19, 0), #M1 + (19, 251), #M1 lbl + (21, 0), #V1 + #(20, 0), #M2 + (20, 251), #M2 lbl + #(25, 0), #V2 + #(30, 0), #M3 + (30, 251), #M3 lbl + #(35, 0), #V3 + #(40, 0), #M4 + (40, 251), #M4 lbl + (45, 0), #V4 + (50, 0), #M5 + (50, 251), #M5 lbl + (55, 0), #V5 + (60, 0), #M6 + (60, 251), #M6 lbl + (65, 0), #V6 + (70, 0), #M7 + (70, 251), #M7 lbl + (75, 0), #V7 + (80, 0), #M8 + (80, 251), #M8 lbl + (85, 0), #V8 + (88, 0), #SDT + (90, 0), #M9 + (90, 251), #M9 lbl + (95, 0), #V9 + (96, 0), #Pad + (97, 0), #SLVT + (98, 0), #LVT + (99, 0), #SRAMDRC + (100, 0), #??? + (101, 0), #??? + (110, 0) #SRAMVT + ] + +print('Opening layout...') +gdspy.LayoutViewer(gds_lib, hidden_types=hidden, depth=1) From 7df5ea68a861df198ae646004c0a5c98d13beaa7 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 7 Oct 2019 06:32:45 +0000 Subject: [PATCH 37/37] Bump FireSim for first batch of AGFIS [ci skip] --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 22ce787f..afd51ab7 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 22ce787fab2515c81bfbc98bbfdcd94b075d7a8a +Subproject commit afd51ab7a847ecb99593077db8d9e369c70242bd