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update parameter classes for RC additions

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This commit is contained in:
Tim Snyder
2020-12-18 23:24:19 +00:00
parent a7e6de835a
commit 72d084da8f
2 changed files with 6 additions and 0 deletions
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4
generators/chipyard/src/main/scala/example/TutorialTile.scala
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@@ -15,6 +15,7 @@ import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._ import freechips.rocketchip.util._
import freechips.rocketchip.tile._ import freechips.rocketchip.tile._
import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.prci.ClockSinkParameters
// Example parameter class copied from CVA6, not included in documentation but for compile check only // Example parameter class copied from CVA6, not included in documentation but for compile check only
// If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure // If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure
@@ -39,6 +40,7 @@ case class MyCoreParams(
val mulDiv: Option[MulDivParams] = Some(MulDivParams()) // copied from Rocket val mulDiv: Option[MulDivParams] = Some(MulDivParams()) // copied from Rocket
val fpu: Option[FPUParams] = Some(FPUParams()) // copied fma latencies from Rocket val fpu: Option[FPUParams] = Some(FPUParams()) // copied fma latencies from Rocket
val nLocalInterrupts: Int = 0 val nLocalInterrupts: Int = 0
val useNMI: Boolean = false
val nPMPs: Int = 0 // TODO: Check val nPMPs: Int = 0 // TODO: Check
val pmpGranularity: Int = 4 // copied from Rocket val pmpGranularity: Int = 4 // copied from Rocket
val nBreakpoints: Int = 0 // TODO: Check val nBreakpoints: Int = 0 // TODO: Check
@@ -51,6 +53,7 @@ case class MyCoreParams(
val misaWritable: Boolean = false val misaWritable: Boolean = false
val haveCFlush: Boolean = false val haveCFlush: Boolean = false
val nL2TLBEntries: Int = 512 // copied from Rocket val nL2TLBEntries: Int = 512 // copied from Rocket
val nL2TLBWays: Int = 1
val mtvecInit: Option[BigInt] = Some(BigInt(0)) // copied from Rocket val mtvecInit: Option[BigInt] = Some(BigInt(0)) // copied from Rocket
val mtvecWritable: Boolean = true // copied from Rocket val mtvecWritable: Boolean = true // copied from Rocket
val instBits: Int = if (useCompressed) 16 else 32 val instBits: Int = if (useCompressed) 16 else 32
@@ -83,6 +86,7 @@ case class MyTileParams(
val boundaryBuffers: Boolean = false val boundaryBuffers: Boolean = false
val dcache: Option[DCacheParams] = Some(DCacheParams()) val dcache: Option[DCacheParams] = Some(DCacheParams())
val icache: Option[ICacheParams] = Some(ICacheParams()) val icache: Option[ICacheParams] = Some(ICacheParams())
val clockSinkParams: ClockSinkParameters = ClockSinkParameters()
def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = { def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = {
new MyTile(this, crossing, lookup) new MyTile(this, crossing, lookup)
} }

2
generators/tracegen/src/main/scala/Tile.scala
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@@ -13,6 +13,7 @@ import freechips.rocketchip.interrupts._
import freechips.rocketchip.subsystem._ import freechips.rocketchip.subsystem._
import boom.lsu.{BoomNonBlockingDCache, LSU, LSUCoreIO} import boom.lsu.{BoomNonBlockingDCache, LSU, LSUCoreIO}
import boom.common.{BoomTileParams, MicroOp, BoomCoreParams, BoomModule} import boom.common.{BoomTileParams, MicroOp, BoomCoreParams, BoomModule}
import freechips.rocketchip.prci.ClockSinkParameters
class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
@@ -190,6 +191,7 @@ case class BoomTraceGenParams(
val blockerCtrlAddr = None val blockerCtrlAddr = None
val name = None val name = None
val traceParams = TraceGenParams(wordBits, addrBits, addrBag, maxRequests, memStart, numGens, dcache, hartId) val traceParams = TraceGenParams(wordBits, addrBits, addrBag, maxRequests, memStart, numGens, dcache, hartId)
val clockSinkParams: ClockSinkParameters = ClockSinkParameters()
} }
class BoomTraceGenTile private( class BoomTraceGenTile private(