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Add GPIO Overlay

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This commit is contained in:
abejgonzalez
2020-09-13 16:37:20 -07:00
parent 69bf39bf13
commit 72c0f4b3d3
5 changed files with 193 additions and 7 deletions
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57
fpga/src/main/scala/vcu118/TestHarness.scala
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@@ -3,9 +3,8 @@ package chipyard.fpga.vcu118
import chisel3._
import chisel3.experimental.{Analog, IO}
import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.config.{Parameters}
import freechips.rocketchip.diplomacy.{InModuleBody, BundleBridgeSource}
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.ip.xilinx._
@@ -15,6 +14,9 @@ import sifive.fpgashells.clocks._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.i2c._
import sifive.blocks.devices.gpio._
import chipyard.fpga.vcu118.bringup._
class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118Shell {
@@ -47,18 +49,44 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
}
/*** SPI ***/
require(p(PeripherySPIKey).size >= 1)
require(p(PeripherySPIKey).size == 2)
// 1st SPI goes to the VCU118 SDIO port
val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(p(PeripherySPIKey).head)))
designParameters(SPIOverlayKey).head.place(SPIDesignInput(p(PeripherySPIKey).head, io_spi_bb))
val sdio_placed = designParameters(SPIOverlayKey).head.place(SPIDesignInput(p(PeripherySPIKey).head, io_spi_bb))
InModuleBody {
topDesign.module match { case dutMod: HasVCU118PlatformIO =>
io_spi_bb.bundle <> dutMod.io_spi.head
}
}
// TODO: No access to the TLSPI node...
//val mmcDev = new MMCDevice(sdio_placed.device, 1)
//ResourceBinding {
// Resource(mmcDev, "reg").bind(ResourceAddress(0))
//}
// 2nd SPI goes to the ADI port
val adi = Overlay(SPIOverlayKey, new chipyard.fpga.vcu118.bringup.BringupSPIVCU118ShellPlacer(this, SPIShellInput()))
val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(p(PeripherySPIKey).last)))
val adi_placed = designParameters(SPIOverlayKey).last.place(SPIDesignInput(p(PeripherySPIKey).last, io_spi_bb_2))
InModuleBody {
topDesign.module match { case dutMod: HasVCU118PlatformIO =>
io_spi_bb_2.bundle <> dutMod.io_spi.last
}
}
// TODO: No access to the TLSPI node...
//val adiDev = new chipyard.fpga.vcu118.bringup.ADISPIDevice(adi_placed.device, 1)
//ResourceBinding {
// Resource(adiDev, "reg").bind(ResourceAddress(0))
//}
/*** I2C ***/
require(p(PeripheryI2CKey).size >= 1)
require(p(PeripheryI2CKey).size == 1)
val i2c = Overlay(I2COverlayKey, new chipyard.fpga.vcu118.bringup.BringupI2CVCU118ShellPlacer(this, I2CShellInput()))
@@ -69,5 +97,24 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
io_i2c_bb.bundle <> dutMod.io_i2c.head
}
}
/*** GPIO ***/
val gpio = Seq.tabulate(p(PeripheryGPIOKey).size)(i => {
val maxGPIOSupport = 32
val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1))
Overlay(GPIOOverlayKey, new chipyard.fpga.vcu118.bringup.BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names))
})
val io_gpio_bb = p(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) }
(designParameters(GPIOOverlayKey) zip p(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) =>
placer.place(GPIODesignInput(params, io_gpio_bb(i)))
}
InModuleBody {
topDesign.module match { case dutMod: HasVCU118PlatformIO =>
(io_gpio_bb zip dutMod.io_gpio).map { case (bb_io, dut_io) =>
bb_io.bundle <> dut_io
}
}
}
}