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Give the PRCI widgets valnames to clean up module naming

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This commit is contained in:
Jerry Zhao
2022-04-06 10:47:04 -07:00
parent 1202cf7632
commit 7290abfa87
1 changed files with 20 additions and 10 deletions
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30
generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
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@@ -29,8 +29,6 @@ case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](Chip
trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles => trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
require(p(SubsystemDriveAsyncClockGroupsKey).isEmpty, "Subsystem asyncClockGroups must be undriven") require(p(SubsystemDriveAsyncClockGroupsKey).isEmpty, "Subsystem asyncClockGroups must be undriven")
implicit val n = ValName("chipyardPRCI")
val prciParams = p(ChipyardPRCIControlKey) val prciParams = p(ChipyardPRCIControlKey)
// Set up clock domain // Set up clock domain
@@ -49,14 +47,17 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
// is created in the ChipTop (the hierarchy wrapping the subsystem), this function // is created in the ChipTop (the hierarchy wrapping the subsystem), this function
// is provided to allow connecting that clock to the clock aggregator. This function // is provided to allow connecting that clock to the clock aggregator. This function
// should be called in the ChipTop context // should be called in the ChipTop context
def connectImplicitClockSinkNode(sink: ClockSinkNode) = def connectImplicitClockSinkNode(sink: ClockSinkNode) = {
val implicitClockGrouper = this { ClockGroup() }
(sink (sink
:= ClockGroup() := implicitClockGrouper
:= aggregator) := aggregator)
}
// 2. The rest of the diplomatic clocks in the subsystem are routed to this asyncClockGroupsNode // 2. The rest of the diplomatic clocks in the subsystem are routed to this asyncClockGroupsNode
val clockNamePrefixer = ClockGroupNamePrefixer()
(asyncClockGroupsNode (asyncClockGroupsNode
:*= ClockGroupNamePrefixer() :*= clockNamePrefixer
:*= aggregator) :*= aggregator)
@@ -68,12 +69,21 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
// 5. Add reset control registers to the tiles (if desired) // 5. Add reset control registers to the tiles (if desired)
// The final clock group here contains physically distinct clock domains, which some PRCI node in a // The final clock group here contains physically distinct clock domains, which some PRCI node in a
// diplomatic IOBinder should drive // diplomatic IOBinder should drive
val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey))
val clockGroupCombiner = ClockGroupCombiner()
val resetSynchronizer = ClockGroupResetSynchronizer()
val tileClockGater = prci_ctrl_domain {
TileClockGater(prciParams.baseAddress + 0x00000, tlbus, prciParams.enableTileClockGating)
}
val tileResetSetter = prci_ctrl_domain {
TileResetSetter(prciParams.baseAddress + 0x10000, tlbus, tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil)
}
(aggregator (aggregator
:= ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey), p(DefaultClockFrequencyKey)) := frequencySpecifier
:= ClockGroupCombiner() := clockGroupCombiner
:= ClockGroupResetSynchronizer() := resetSynchronizer
:= prci_ctrl_domain { TileClockGater(prciParams.baseAddress + 0x00000, tlbus, prciParams.enableTileClockGating) } := tileClockGater
:= prci_ctrl_domain { TileResetSetter(prciParams.baseAddress + 0x10000, tlbus, tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil) } := tileResetSetter
:= allClockGroupsNode) := allClockGroupsNode)
} }