wu-arch/chipyard
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Print full stack traces (default traceLevel = 0) | Bump FireSim

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abejgonzalez
2020-12-03 14:57:05 -08:00
parent d0079a9659
commit 70fa0a037d
2 changed files with 1 additions and 5 deletions
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4
build.sbt
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@@ -1,8 +1,5 @@
import Tests._ import Tests._
// Ignore linting for traceLevel
Global / excludeLintKeys += traceLevel
// This gives us a nicer handle to the root project instead of using the // This gives us a nicer handle to the root project instead of using the
// implicit one // implicit one
lazy val chipyardRoot = Project("chipyardRoot", file(".")) lazy val chipyardRoot = Project("chipyardRoot", file("."))
@@ -11,7 +8,6 @@ lazy val commonSettings = Seq(
organization := "edu.berkeley.cs", organization := "edu.berkeley.cs",
version := "1.3", version := "1.3",
scalaVersion := "2.12.10", scalaVersion := "2.12.10",
traceLevel := 15,
test in assembly := {}, test in assembly := {},
assemblyMergeStrategy in assembly := { _ match { assemblyMergeStrategy in assembly := { _ match {
case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard

2
sims/firesim

Submodule sims/firesim updated: 6dc98f6cff...2addd72598