Address generator unification PR reviews

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -24,26 +24,26 @@ import tracegen.HasTraceGenTilesModuleImp
 
 import boom.common.{BoomTile}
 
-import chipyard.iobinders.{IOBinders, RegisterIOBinder, RegisterBinder}
+import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder}
 import chipyard.HasBoomAndRocketTilesModuleImp
 
-class WithSerialBridge extends RegisterIOBinder({
+class WithSerialBridge extends OverrideIOBinder({
   (c, r, s, target: CanHavePeripherySerialModuleImp) => target.serial.map(s => SerialBridge(s)(target.p)).toSeq
 })
 
-class WithNICBridge extends RegisterIOBinder({
+class WithNICBridge extends OverrideIOBinder({
   (c, r, s, target: CanHavePeripheryIceNICModuleImp) => target.net.map(n => NICBridge(n)(target.p)).toSeq
 })
 
-class WithUARTBridge extends RegisterIOBinder({
+class WithUARTBridge extends OverrideIOBinder({
   (c, r, s, target: HasPeripheryUARTModuleImp) => target.uart.map(u => UARTBridge(u)(target.p)).toSeq
 })
 
-class WithBlockDeviceBridge extends RegisterIOBinder({
+class WithBlockDeviceBridge extends OverrideIOBinder({
   (c, r, s, target: CanHavePeripheryBlockDeviceModuleImp) => target.bdev.map(b => BlockDevBridge(b, target.reset.toBool)(target.p)).toSeq
 })
 
-class WithFASEDBridge extends RegisterIOBinder({
+class WithFASEDBridge extends OverrideIOBinder({
   (c, r, s, t: CanHaveMasterAXI4MemPortModuleImp) => {
     implicit val p = t.p
     (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) =>
@@ -58,15 +58,15 @@ class WithFASEDBridge extends RegisterIOBinder({
   }
 })
 
-class WithTracerVBridge extends RegisterIOBinder({
+class WithTracerVBridge extends OverrideIOBinder({
   (c, r, s, target: CanHaveTraceIOModuleImp) => target.traceIO.map(t => TracerVBridge(t)(target.p)).toSeq
 })
 
-class WithTraceGenBridge extends RegisterIOBinder({
+class WithTraceGenBridge extends OverrideIOBinder({
   (c, r, s, target: HasTraceGenTilesModuleImp) => Seq(GroundTestBridge(target.success)(target.p))
 })
 
-class WithFireSimMultiCycleRegfile extends RegisterBinder({
+class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
   (c, r, s, target: HasBoomAndRocketTilesModuleImp) => {
     target.outer.tiles.map {
       case r: RocketTile => {

generators/firechip/src/main/scala/FireSim.scala

@@ -0,0 +1,38 @@
+//See LICENSE for license details.
+
+package firesim.firesim
+
+import chisel3._
+
+import freechips.rocketchip.config.{Field, Config, Parameters}
+import freechips.rocketchip.diplomacy.{LazyModule}
+
+import midas.widgets.{Bridge, PeekPokeBridge}
+
+import chipyard.{BuildTop}
+import chipyard.iobinders.{IOBinders}
+
+// Determines the number of times to instantiate the DUT in the harness.
+// Subsumes legacy supernode support
+case object NumNodes extends Field[Int](1)
+
+class WithNumNodes(n: Int) extends Config((pname, site, here) => {
+  case NumNodes => n
+})
+
+class FireSim(implicit val p: Parameters) extends RawModule {
+  val clock = IO(Input(Clock()))
+  val reset = WireInit(false.B)
+  withClockAndReset(clock, reset) {
+    // Instantiate multiple instances of the DUT to implement supernode
+    val targets = Seq.fill(p(NumNodes))(p(BuildTop)(p))
+    val peekPokeBridge = PeekPokeBridge(reset)
+    // A Seq of partial functions that will instantiate the right bridge only
+    // if that Mixin trait is present in the target's class instance
+    //
+    // Apply each partial function to each DUT instance
+    for ((target) <- targets) {
+      p(IOBinders).values.map(fn => fn(false.B, target))
+    }
+  }
+}

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -21,7 +21,6 @@ import tracegen.TraceGenKey
 import icenet._
 
 import firesim.bridges._
-import firesim.util.{WithNumNodes}
 import firesim.configs._
 import chipyard.{BuildTop}
 import chipyard.config.ConfigValName._
@@ -106,11 +105,13 @@ class WithFireSimConfigTweaks extends Config(
 //*****************************************************************
 // Rocket configs, base off chipyard's RocketConfig
 //*****************************************************************
+// DOC include start: firesimconfig
 class FireSimRocketConfig extends Config(
   new WithDefaultFireSimBridges ++
   new WithDefaultMemModel ++
   new WithFireSimConfigTweaks ++
   new chipyard.RocketConfig)
+// DOC include end: firesimconfig
 
 class FireSimQuadRocketConfig extends Config(
   new WithDefaultFireSimBridges ++
@@ -119,19 +120,6 @@ class FireSimQuadRocketConfig extends Config(
   new chipyard.QuadRocketConfig)
 
 
-//*****************************************************************
-// Sha3 rocc-accel configs, base off chipyard's Sha3RocketConfig
-//*****************************************************************
-class FireSimSha3RocketConfig extends Config(
-  new WithDefaultFireSimBridges ++
-  new WithDefaultMemModel ++
-  new WithFireSimConfigTweaks ++
-  new chipyard.Sha3RocketConfig)
-
-class FireSimSha3PrintfRocketConfig extends Config(
-  new sha3.WithSha3Printf ++
-  new FireSimSha3RocketConfig)
-
 //*****************************************************************
 // Boom config, base off chipyard's LargeBoomConfig
 //*****************************************************************

generators/firechip/src/main/scala/Targets.scala

@@ -1,43 +0,0 @@
-package firesim.firesim
-
-import chisel3._
-import freechips.rocketchip._
-import freechips.rocketchip.subsystem._
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.tilelink._
-import freechips.rocketchip.devices.tilelink._
-import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
-import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.util.{HeterogeneousBag}
-import freechips.rocketchip.amba.axi4.AXI4Bundle
-import freechips.rocketchip.config.{Field, Parameters}
-import freechips.rocketchip.diplomacy.LazyModule
-import icenet._
-import firesim.util.DefaultFireSimHarness
-import testchipip._
-import testchipip.SerialAdapter.SERIAL_IF_WIDTH
-import tracegen.{HasTraceGenTiles, HasTraceGenTilesModuleImp}
-import sifive.blocks.devices.uart._
-import java.io.File
-
-
-object FireSimValName {
-  implicit val valName = ValName("FireSimHarness")
-}
-import FireSimValName._
-
-
-
-/*******************************************************************************
-* Top level DESIGN configurations. These describe the basic instantiations of
-* the designs being simulated.
-*
-* In general, if you're adding or removing features from any of these, you
-* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager
-* will store this name as part of the tags for the AGFI, so that later you can
-* reconstruct what is in a particular AGFI. These tags are also used to
-* determine which driver to build.
-*******************************************************************************/
-
-
-class FireSim(implicit p: Parameters) extends DefaultFireSimHarness