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Fix verilator makefile

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Zitao Fang
2020-08-14 17:52:36 -07:00
parent b3fe2cae24
commit 700f68730b
1 changed files with 1 additions and 1 deletions
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sims/verilator/Makefile
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@@ -28,7 +28,7 @@ sim_prefix = simulator
sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
WAVEFORM_FLAG=-v$(sim_out_name).vcd
WAVEFORM_FLAG=-v $(sim_out_name).vcd
# If verilator seed unspecified, verilator uses srand as random seed
ifdef RANDOM_SEED