replace DefaultBusConfiguration trait with HierarchicalBusTopology trait from FireSim

generators/firechip/src/main/scala/TargetMixins.scala

@@ -14,30 +14,6 @@ import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction}
 import midas.models.AXI4BundleWithEdge
 import midas.targetutils.ExcludeInstanceAsserts
 
-/** Ties together Subsystem buses in the same fashion done in the example top of Rocket Chip */
-trait HasDefaultBusConfiguration {
-  this: BaseSubsystem =>
-  // The sbus masters the cbus; here we convert TL-UH -> TL-UL
-  sbus.crossToBus(cbus, NoCrossing)
-
-  // The cbus masters the pbus; which might be clocked slower
-  cbus.crossToBus(pbus, SynchronousCrossing())
-
-  // The fbus masters the sbus; both are TL-UH or TL-C
-  FlipRendering { implicit p =>
-    sbus.crossFromBus(fbus, SynchronousCrossing())
-  }
-
-  // The sbus masters the mbus; here we convert TL-C -> TL-UH
-  private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key)
-  private val (in, out, halt) = coherenceManager(this)
-  if (nBanks != 0) {
-    sbus.coupleTo("coherence_manager") { in :*= _ }
-    mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out }
-  }
-}
-
-
 /** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges
   *  associated with each port. This drives FASED functional model sizing
   */