updated tutorial configuration files [skip ci]
This commit is contained in:
Nayiri K
@@ -2,149 +2,18 @@
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# Specify clock signals
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vlsi.inputs.clocks: [
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{name: "clock_clock", period: "5ns", uncertainty: "1ns"}
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{name: "clock_clock", period: "30ns", uncertainty: "2ns"}
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]
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# Power Straps
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par.power_straps_mode: generate
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par.generate_power_straps_method: by_tracks
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par.blockage_spacing: 40.0
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par.blockage_spacing_top_layer: met4
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par.generate_power_straps_options:
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by_tracks:
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strap_layers:
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- met4
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- met5
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pin_layers:
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- met5
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blockage_spacing_met2: 4.0
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blockage_spacing_met4: 2.0
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track_width: 3
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track_width_met5: 1
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track_spacing: 5
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track_start: 10
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track_start_met5: 1
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power_utilization: 0.1
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power_utilization_met4: 0.1
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power_utilization_met5: 0.1
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# Placement Constraints
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vlsi.inputs.placement_constraints:
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- path: "ChipTop"
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type: toplevel
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x: 0
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y: 0
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width: 4000
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height: 2500
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margins:
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left: 0
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right: 0
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top: 0
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bottom: 0
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# Place data cache SRAM instances
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
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type: hardmacro
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x: 50
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y: 100
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orientation: r0
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
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type: hardmacro
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x: 50
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y: 700
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orientation: r0
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0"
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type: hardmacro
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x: 50
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y: 1300
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orientation: r0
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0"
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type: hardmacro
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x: 50
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y: 1900
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orientation: r0
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0"
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type: hardmacro
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x: 1000
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y: 1900
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orientation: r0
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0"
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type: hardmacro
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x: 1000
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y: 1300
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orientation: r0
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0"
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type: hardmacro
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x: 1000
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y: 700
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orientation: r0
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0"
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type: hardmacro
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x: 1000
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y: 100
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orientation: r0
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# Place instruction cache SRAM instances
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
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type: hardmacro
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x: 3250
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y: 100
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orientation: r0
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0"
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type: hardmacro
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x: 3250
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y: 700
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orientation: r0
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
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type: hardmacro
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x: 3450
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y: 1300
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orientation: r0
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# Place L2 TLB SRAM instances
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
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type: hardmacro
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x: 2000
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y: 1300
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orientation: "r0"
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1"
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type: hardmacro
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x: 2000
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y: 1900
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orientation: "r0"
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2"
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type: hardmacro
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x: 2750
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y: 1300
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orientation: "r0"
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3"
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type: hardmacro
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x: 2750
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y: 1900
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orientation: "r0"
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- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4"
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type: hardmacro
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x: 3460
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y: 1900
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orientation: "r0"
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# Pin placement constraints
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vlsi.inputs.pin_mode: generated
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vlsi.inputs.pin.generate_mode: semi_auto
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vlsi.inputs.pin.assignments: [
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{pins: "*", layers: ["met2", "met4"], side: "bottom"}
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]
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# If overriding the placement constraints in example-sky130.yml,
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# ensure one of the toplevel margin sides corresponding with the power pin metal layers
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# is set to 0 so that Innovus actually creates those pins (otherwise LVS will fail).
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# For example, in example-sky130.yml we set
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# par.generate_power_straps_options.by_tracks.pin_layers: 'met5' # horizontal layer
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# therefore we must also set:
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# vlsi.inputs.placement_constraints:
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# - path: "ChipTop"
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# ...
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# margins:
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# right: 0 # or left: 0
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@@ -3,88 +3,37 @@
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# Specify clock signals
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# Relax the clock period for OpenROAD to meet timing
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vlsi.inputs.clocks: [
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{name: "clock_clock", period: "30ns", uncertainty: "1ns"}
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{name: "clock_clock", period: "50ns", uncertainty: "2ns"}
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]
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# Placement Constraints
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vlsi.inputs.placement_constraints:
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- path: "ChipTop"
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type: toplevel
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x: 0
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y: 0
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width: 4000
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height: 2500
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margins:
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left: 10
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right: 10
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top: 10
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bottom: 10
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# Flow parameters that yield a routable design with reasonable timing
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par.openroad:
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timing_driven: true # set to false to drastically speed up runs
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create_archive_mode: none
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# Place data cache SRAM instances
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_0"
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type: hardmacro
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x: 50
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y: 100
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orientation: r0
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write_reports: true # set to false to slightly speed up runs
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_0"
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type: hardmacro
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x: 50
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y: 700
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orientation: r0
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floorplan_mode: generate
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_0"
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type: hardmacro
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x: 50
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y: 1300
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orientation: r0
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macro_placement.halo: [50, 50]
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_0"
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type: hardmacro
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x: 50
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y: 1900
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orientation: r0
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global_placement.timing_driven: true
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global_placement.routability_driven: true
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_4_0"
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type: hardmacro
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x: 1000
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y: 1900
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orientation: r0
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global_placement.placement_padding: 6
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detailed_placement.placement_padding: 4
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clock_tree.placement_padding: 2
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clock_tree_resize.placement_padding: 0
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clock_tree_resize.setup_margin: 0.0
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clock_tree_resize.hold_margin: 0.20
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global_route_resize.hold_margin: 0.60
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clock_tree_resize.hold_max_buffer_percent: 80
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_5_0"
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type: hardmacro
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x: 1000
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y: 1300
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orientation: r0
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global_placement.routing_adjustment: 0.5
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global_route.routing_adjustment: 0.3
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global_route_resize.routing_adjustment: 0.2
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_6_0"
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type: hardmacro
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x: 1000
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y: 700
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orientation: r0
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_7_0"
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type: hardmacro
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x: 1000
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y: 100
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orientation: r0
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# Place instruction cache SRAM instances
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_0_0"
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type: hardmacro
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x: 3250
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y: 100
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orientation: r0
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_1_0"
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type: hardmacro
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x: 3250
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y: 700
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orientation: r0
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.tag_array.tag_array_ext.mem_0_0"
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type: hardmacro
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x: 3450
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y: 1300
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orientation: r0
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# DRC/LVS configuration
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drc.magic.generate_only: true
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lvs.netgen.generate_only: true
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