From fba75e7a74d57beec00a91ff334dbdb8cf7af251 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 19 Oct 2023 23:40:33 -0700 Subject: [PATCH 1/8] Bump constellation with improved TL-noc --- .../src/main/scala/config/NoCConfigs.scala | 71 +++++++++++++++---- .../main/scala/config/TutorialConfigs.scala | 8 +-- generators/constellation | 2 +- 3 files changed, 64 insertions(+), 17 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala index 0b6be558..166050c7 100644 --- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala @@ -6,6 +6,7 @@ import freechips.rocketchip.subsystem.{SBUS, MBUS} import constellation.channel._ import constellation.routing._ +import constellation.router._ import constellation.topology._ import constellation.noc._ import constellation.soc.{GlobalNoCParams} @@ -62,19 +63,19 @@ import scala.collection.immutable.ListMap */ // DOC include start: MultiNoCConfig class MultiNoCConfig extends Config( - new constellation.soc.WithCbusNoC(constellation.protocol.TLNoCParams( + new constellation.soc.WithCbusNoC(constellation.protocol.SimpleTLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap( "serial-tl" -> 0), outNodeMapping = ListMap( - "error" -> 1, "l2[0]" -> 2, "pbus" -> 3, "plic" -> 4, + "error" -> 1, "ctrls[0]" -> 2, "pbus" -> 3, "plic" -> 4, "clint" -> 5, "dmInner" -> 6, "bootrom" -> 7, "clock" -> 8)), NoCParams( topology = TerminalRouter(BidirectionalLine(9)), channelParamGen = (a, b) => UserChannelParams(Seq.fill(5) { UserVirtualChannelParams(4) }), routingRelation = NonblockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalLineRouting()), 5, 1)) )) ++ - new constellation.soc.WithMbusNoC(constellation.protocol.TLNoCParams( + new constellation.soc.WithMbusNoC(constellation.protocol.SimpleTLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap( "L2 InclusiveCache[0]" -> 1, "L2 InclusiveCache[1]" -> 2, @@ -87,7 +88,7 @@ class MultiNoCConfig extends Config( channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }), routingRelation = BlockingVirtualSubnetworksRouting(TerminalRouterRouting(BidirectionalTorus1DShortestRouting()), 5, 2)) )) ++ - new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams( + new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap( "Core 0" -> 1, "Core 1" -> 2, "Core 2" -> 4 , "Core 3" -> 7, @@ -162,15 +163,15 @@ class SharedNoCConfig extends Config( BidirectionalLineRouting()))), 10, 2) ) )) ++ - new constellation.soc.WithMbusNoC(constellation.protocol.TLNoCParams( + new constellation.soc.WithMbusNoC(constellation.protocol.GlobalTLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap( "Cache[0]" -> 0, "Cache[1]" -> 2, "Cache[2]" -> 8, "Cache[3]" -> 6), outNodeMapping = ListMap( "system[0]" -> 3, "system[1]" -> 5, "serdesser" -> 9)) - ), true) ++ - new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams( + )) ++ + new constellation.soc.WithSbusNoC(constellation.protocol.GlobalTLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap( "serial-tl" -> 9, "Core 0" -> 2, @@ -179,7 +180,7 @@ class SharedNoCConfig extends Config( outNodeMapping = ListMap( "system[0]" -> 0, "system[1]" -> 2, "system[2]" -> 8, "system[3]" -> 6, "pbus" -> 4)) - ), true) ++ + )) ++ new freechips.rocketchip.subsystem.WithNBigCores(8) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++ @@ -188,7 +189,7 @@ class SharedNoCConfig extends Config( // DOC include end: SharedNoCConfig class SbusRingNoCConfig extends Config( - new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams( + new constellation.soc.WithSbusNoC(constellation.protocol.SplitACDxBETLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap( "Core 0" -> 0, @@ -206,12 +207,58 @@ class SbusRingNoCConfig extends Config( "system[2]" -> 11, "system[3]" -> 12, "pbus" -> 8)), // TSI is on the pbus, so serial-tl and pbus should be on the same node - NoCParams( + acdNoCParams = NoCParams( topology = UnidirectionalTorus1D(13), - channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }), - routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 5, 2)) + channelParamGen = (a, b) => UserChannelParams(Seq.fill(6) { UserVirtualChannelParams(4) }), + routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 3, 2)), + beNoCParams = NoCParams( + topology = UnidirectionalTorus1D(13), + channelParamGen = (a, b) => UserChannelParams(Seq.fill(4) { UserVirtualChannelParams(1) }), + routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 2, 2)) )) ++ new freechips.rocketchip.subsystem.WithNBigCores(8) ++ new freechips.rocketchip.subsystem.WithNBanks(4) ++ new chipyard.config.AbstractConfig ) + +class SbusMeshNoCConfig extends Config( + new constellation.soc.WithSbusNoC(constellation.protocol.SplitACDxBETLNoCParams( + constellation.protocol.DiplomaticNetworkNodeMapping( + inNodeMapping = ListMap( + "Core 0 " -> 0, + "Core 1 " -> 1, + "Core 2 " -> 2, + "Core 3 " -> 3, + "Core 4 " -> 4, + "Core 5 " -> 7, + "Core 6 " -> 8, + "Core 7 " -> 11, + "Core 8 " -> 12, + "Core 9 " -> 13, + "Core 10 " -> 14, + "Core 11 " -> 15, + "serial-tl" -> 0), + outNodeMapping = ListMap( + "system[0]" -> 5, + "system[1]" -> 6, + "system[2]" -> 9, + "system[3]" -> 10, + "pbus" -> 0)), // TSI is on the pbus, so serial-tl and pbus should be on the same node + acdNoCParams = NoCParams( + topology = Mesh2D(4, 4), + channelParamGen = (a, b) => UserChannelParams(Seq.fill(3) { UserVirtualChannelParams(3) }, unifiedBuffer = false), + routerParams = (i) => UserRouterParams(combineRCVA=true, combineSAST=true), + routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 3, 1)), + beNoCParams = NoCParams( + topology = Mesh2D(4, 4), + channelParamGen = (a, b) => UserChannelParams(Seq.fill(2) { UserVirtualChannelParams(3) }, unifiedBuffer = false), + routerParams = (i) => UserRouterParams(combineRCVA=true, combineSAST=true), + routingRelation = NonblockingVirtualSubnetworksRouting(Mesh2DDimensionOrderedRouting(), 2, 1)), + beDivision = 4 + )) ++ + new freechips.rocketchip.subsystem.WithNBigCores(12) ++ + new freechips.rocketchip.subsystem.WithNBanks(4) ++ + new chipyard.config.WithSystemBusWidth(128) ++ + new chipyard.config.AbstractConfig +) + diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index daa08265..9803c935 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -90,14 +90,14 @@ class TutorialNoCConfig extends Config( // The inNodeMapping and outNodeMapping values are the physical identifiers of // routers on the topology to map the agents to. Try changing these to any // value within the range [0, topology.nNodes) - new constellation.soc.WithPbusNoC(constellation.protocol.TLNoCParams( + new constellation.soc.WithPbusNoC(constellation.protocol.GlobalTLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap("Core" -> 7), outNodeMapping = ListMap( "pbus" -> 8, "uart" -> 9, "control" -> 10, "gcd" -> 11, "writeQueue[0]" -> 0, "writeQueue[1]" -> 1, "tailChain[0]" -> 2)) - ), true) ++ - new constellation.soc.WithSbusNoC(constellation.protocol.TLNoCParams( + )) ++ + new constellation.soc.WithSbusNoC(constellation.protocol.GlobalTLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( inNodeMapping = ListMap( "Core 0" -> 0, "Core 1" -> 1, @@ -105,7 +105,7 @@ class TutorialNoCConfig extends Config( outNodeMapping = ListMap( "system[0]" -> 3, "system[1]" -> 4, "system[2]" -> 5, "system[3]" -> 6, "pbus" -> 7)) - ), true) ++ + )) ++ new chipyard.example.WithGCD ++ new chipyard.harness.WithLoopbackNIC ++ new icenet.WithIceNIC ++ diff --git a/generators/constellation b/generators/constellation index 03ed9e4e..4eb05203 160000 --- a/generators/constellation +++ b/generators/constellation @@ -1 +1 @@ -Subproject commit 03ed9e4ecd31d71d4bd48f02b0e806bc2b8a7e6b +Subproject commit 4eb052037d00606f9642b8341f051a73b3e84aa0 From 088e9ea45a4c9d00555f4a1fe087a5cc11875ad9 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 13 Dec 2023 10:07:14 -0800 Subject: [PATCH 2/8] Remove references to ENABLE_YOSYS --- common.mk | 1 - docs/VLSI/Sky130-Commercial-Tutorial.rst | 3 +-- docs/VLSI/Sky130-OpenROAD-Tutorial.rst | 8 +++----- vlsi/example-designs/sky130-openroad-rockettile.yml | 2 -- vlsi/example-designs/sky130-openroad.yml | 2 -- vlsi/tutorial.mk | 3 --- 6 files changed, 4 insertions(+), 15 deletions(-) diff --git a/common.mk b/common.mk index 5e0e2fcd..f525b526 100644 --- a/common.mk +++ b/common.mk @@ -28,7 +28,6 @@ EXTRA_SIM_CXXFLAGS ?= EXTRA_SIM_LDFLAGS ?= EXTRA_SIM_SOURCES ?= EXTRA_SIM_REQS ?= -ENABLE_CUSTOM_FIRRTL_PASS += $(ENABLE_YOSYS_FLOW) ifneq ($(ASPECTS), ) comma = , diff --git a/docs/VLSI/Sky130-Commercial-Tutorial.rst b/docs/VLSI/Sky130-Commercial-Tutorial.rst index 70be799e..92e4330c 100644 --- a/docs/VLSI/Sky130-Commercial-Tutorial.rst +++ b/docs/VLSI/Sky130-Commercial-Tutorial.rst @@ -123,8 +123,7 @@ The ``buildfile`` make target has dependencies on both (1) the Verilog that is e and (2) the mapping of memory instances in the design to SRAM macros; all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory. Note that the files in ``generated-src`` vary for each tool/technology flow. -This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows -(due to the ``ENABLE_YOSYS_FLOW`` flag present for the OpenROAD flow), so these flows should be run in separate +This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows, so these flows should be run in separate chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly. diff --git a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst index f9bbbffb..0c138d66 100644 --- a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst +++ b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst @@ -49,7 +49,7 @@ Prerequisites * OpenROAD flow tools (NOTE: tutorial may break with different tool versions): * **Yosys 0.27+3** (synthesis), install `using conda `__ or `from source `__ - * **OpenROAD v2.0-7070-g0264023b6** (place-and-route), install `using conda `__ (note that GUI is disabled in conda package) or + * **OpenROAD v2.0-7070-g0264023b6** (place-and-route), install `using conda `__ (note that GUI is disabled in conda package) or `from source `__ (git hash: 0264023b6c2a8ae803b8d440478d657387277d93) * **KLayout 0.28.5** (DEF to GDSII conversion, DRC), install `using conda `__ or `from source `__ * **Magic 8.3.376** (DRC), install `using conda `__ or `from source `__ @@ -161,8 +161,7 @@ The ``buildfile`` make target has dependencies on both (1) the Verilog that is e and (2) the mapping of memory instances in the design to SRAM macros; all files related to these two steps reside in the ``generated-src/chipyard.harness.TestHarness.TinyRocketConfig-ChipTop`` directory. Note that the files in ``generated-src`` vary for each tool/technology flow. -This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows -(due to the ``ENABLE_YOSYS_FLOW`` flag, explained below), so these flows should be run in separate +This especially applies to the Sky130 Commercial vs OpenROAD tutorial flows, so these flows should be run in separate chipyard installations. If the wrong sources are generated, simply run ``make buildfile -B`` to rebuild all targets correctly. @@ -175,7 +174,6 @@ which will cause additional variables to be set in ``tutorial.mk``, a few of whi * ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml`` * ``VLSI_OBJ_DIR=build-sky130-openroad`` gives the build directory a unique name to allow running multiple flows in the same repo. Note that for the rest of the tutorial we will still refer to this directory in file paths as ``build``, again for brevity. * ``VLSI_TOP`` is by default ``ChipTop``, which is the name of the top-level Verilog module generated in the Chipyard SoC configs. By instead setting ``VLSI_TOP=Rocket``, we can use the Rocket core as the top-level module for the VLSI flow, which consists only of a single RISC-V core (and no caches, peripherals, buses, etc). This is useful to run through this tutorial quickly, and does not rely on any SRAMs. -* ``ENABLE_YOSYS_FLOW = 1`` is required for synthesis through Yosys. This reverts to the Scala FIRRTL Compiler so that unsupported multidimensional arrays are not generated in the Verilog. Running the VLSI Flow --------------------- @@ -275,7 +273,7 @@ This is because Magic and Netgen, as of the writing of this tutorial, do not hav so to view the DRC/LVS results for debugging you must launch the tool interactively, then run DRC/LVS checks, which is done by the ``generated-scripts/view_[drc|lvs]`` scripts. This is not the case for KLayout, which does have a loadable database format. -Below is the window you should see when loading the KLayout DRC results interactively. Note that most of these DRC errors are +Below is the window you should see when loading the KLayout DRC results interactively. Note that most of these DRC errors are from special rules relating to Sky130 SRAMs, which have been verified separately. In the future the KLayout tool plugin should blackbox these SRAM macros by default, but this feature does not exist yet. diff --git a/vlsi/example-designs/sky130-openroad-rockettile.yml b/vlsi/example-designs/sky130-openroad-rockettile.yml index c7300f9b..7db35c9b 100644 --- a/vlsi/example-designs/sky130-openroad-rockettile.yml +++ b/vlsi/example-designs/sky130-openroad-rockettile.yml @@ -22,8 +22,6 @@ vlsi.inputs.placement_constraints: bottom: 10 # Place SRAM memory instances - # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag - # data cache - path: "RocketTile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 50 diff --git a/vlsi/example-designs/sky130-openroad.yml b/vlsi/example-designs/sky130-openroad.yml index 33f01cad..3b95d982 100644 --- a/vlsi/example-designs/sky130-openroad.yml +++ b/vlsi/example-designs/sky130-openroad.yml @@ -54,8 +54,6 @@ vlsi.inputs.placement_constraints: bottom: 10 # Place SRAM memory instances - # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag - # data cache - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 50 diff --git a/vlsi/tutorial.mk b/vlsi/tutorial.mk index 92ba0a98..ddafd80f 100644 --- a/vlsi/tutorial.mk +++ b/vlsi/tutorial.mk @@ -39,7 +39,4 @@ ifeq ($(tutorial),sky130-openroad) example-designs/sky130-openroad-rockettile.yml, ) VLSI_OBJ_DIR ?= build-sky130-openroad INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS) - # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time. - ENABLE_YOSYS_FLOW = 1 endif - From 94b52baad1bfaaf38f6406edad4fb3be1a71161e Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 14 Dec 2023 11:20:02 -0800 Subject: [PATCH 3/8] Add comments on sbus noc-configs --- generators/chipyard/src/main/scala/config/NoCConfigs.scala | 3 +++ 1 file changed, 3 insertions(+) diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala index 166050c7..3e2f5541 100644 --- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala +++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala @@ -188,6 +188,7 @@ class SharedNoCConfig extends Config( ) // DOC include end: SharedNoCConfig +// This Config implements a simple ring interconnect for the system bus class SbusRingNoCConfig extends Config( new constellation.soc.WithSbusNoC(constellation.protocol.SplitACDxBETLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( @@ -221,6 +222,8 @@ class SbusRingNoCConfig extends Config( new chipyard.config.AbstractConfig ) +// This config integrates a mesh interconnect for the system bus, and divides the system bus +// tilelink messages across two isolated interconnects class SbusMeshNoCConfig extends Config( new constellation.soc.WithSbusNoC(constellation.protocol.SplitACDxBETLNoCParams( constellation.protocol.DiplomaticNetworkNodeMapping( From cfa22d1a51da3732750b96ee41026e084191ddfc Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 14 Dec 2023 11:20:56 -0800 Subject: [PATCH 4/8] Bump constellation --- generators/constellation | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/constellation b/generators/constellation index 4eb05203..3632183f 160000 --- a/generators/constellation +++ b/generators/constellation @@ -1 +1 @@ -Subproject commit 4eb052037d00606f9642b8341f051a73b3e84aa0 +Subproject commit 3632183fd1171d00c7f78b32c305841d231031b7 From 42622919cd4833a20db2d36d1646a313a34fe966 Mon Sep 17 00:00:00 2001 From: Nayiri Date: Thu, 14 Dec 2023 18:02:32 -0800 Subject: [PATCH 5/8] fixing macro paths for yosys with circt generated verilog [skip ci] --- .../sky130-openroad-rockettile.yml | 19 +++++-------------- vlsi/example-sky130.yml | 5 +++++ vlsi/tutorial.mk | 2 ++ 3 files changed, 12 insertions(+), 14 deletions(-) diff --git a/vlsi/example-designs/sky130-openroad-rockettile.yml b/vlsi/example-designs/sky130-openroad-rockettile.yml index 7db35c9b..4a6b664c 100644 --- a/vlsi/example-designs/sky130-openroad-rockettile.yml +++ b/vlsi/example-designs/sky130-openroad-rockettile.yml @@ -22,25 +22,16 @@ vlsi.inputs.placement_constraints: bottom: 10 # Place SRAM memory instances - - path: "RocketTile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" + # data cache + - path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" type: hardmacro x: 50 y: 50 orientation: r90 - - path: "RocketTile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0" + - path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" type: hardmacro x: 50 - y: 450 - orientation: r90 - - path: "RocketTile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0" - type: hardmacro - x: 50 - y: 850 - orientation: r90 - - path: "RocketTile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0" - type: hardmacro - x: 50 - y: 1250 + y: 800 orientation: r90 # tag array @@ -51,7 +42,7 @@ vlsi.inputs.placement_constraints: orientation: r90 # instruction cache - - path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0" + - path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 50 y: 2100 diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml index 1cd281f7..1e3faf1c 100644 --- a/vlsi/example-sky130.yml +++ b/vlsi/example-sky130.yml @@ -48,6 +48,11 @@ vlsi.inputs.placement_constraints: x: 50 y: 50 orientation: r90 + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" + type: hardmacro + x: 50 + y: 800 + orientation: r90 # tag array - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" diff --git a/vlsi/tutorial.mk b/vlsi/tutorial.mk index ddafd80f..5e57455f 100644 --- a/vlsi/tutorial.mk +++ b/vlsi/tutorial.mk @@ -39,4 +39,6 @@ ifeq ($(tutorial),sky130-openroad) example-designs/sky130-openroad-rockettile.yml, ) VLSI_OBJ_DIR ?= build-sky130-openroad INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS) + # Yosys compatibility for CIRCT-generated Verilog + ENABLE_YOSYS_FLOW = 1 endif From 93d7c511f90708c1f154b089e76f9d8e830cf61f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 15 Dec 2023 16:10:46 -0800 Subject: [PATCH 6/8] replace-content.py should use python3 explicitly --- scripts/replace-content.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/replace-content.py b/scripts/replace-content.py index 4699ccca..a20acaa8 100755 --- a/scripts/replace-content.py +++ b/scripts/replace-content.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python +#!/usr/bin/env python3 # Replace text in a file given a key identifying a block to replace. # If the file doesn't exist, create it. From d1822c04e27aa2b1e5e5629eac4db7a5ce0f3fd2 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Mon, 11 Dec 2023 17:06:00 -0800 Subject: [PATCH 7/8] Bump spike --- toolchains/riscv-tools/riscv-isa-sim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim index 5a499ef7..4d8651be 160000 --- a/toolchains/riscv-tools/riscv-isa-sim +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 5a499ef718bba2fc323e9771ebd7545c66825ff6 +Subproject commit 4d8651be943ea706eb8dcb3443add2e7ccc117a6 From 6bf915a89c9861cba3fc965f47a58f6d1cb4d796 Mon Sep 17 00:00:00 2001 From: joey0320 Date: Mon, 11 Dec 2023 17:11:45 -0800 Subject: [PATCH 8/8] Add spike-devices as a submodule --- .gitmodules | 3 +++ docs/Software/Spike.rst | 21 ++++++++++++++++ .../src/main/resources/csrc/spiketile.cc | 25 ++++++++++--------- generators/testchipip | 2 +- scripts/build-toolchain-extra.sh | 6 +++++ toolchains/riscv-tools/riscv-spike-devices | 1 + 6 files changed, 45 insertions(+), 13 deletions(-) create mode 160000 toolchains/riscv-tools/riscv-spike-devices diff --git a/.gitmodules b/.gitmodules index db0837ec..e1768873 100644 --- a/.gitmodules +++ b/.gitmodules @@ -142,3 +142,6 @@ [submodule "tools/install-circt"] path = tools/install-circt url = https://github.com/circt/install-circt/ +[submodule "toolchains/riscv-tools/riscv-spike-devices"] + path = toolchains/riscv-tools/riscv-spike-devices + url = https://github.com/ucb-bar/spike-devices.git diff --git a/docs/Software/Spike.rst b/docs/Software/Spike.rst index e9abe0c0..10fa8429 100644 --- a/docs/Software/Spike.rst +++ b/docs/Software/Spike.rst @@ -50,3 +50,24 @@ Spike-as-a-Tile can be configured with custom IPC, commit logging, and other beh * ``+spike-fast-clint``: Enables fast-forwarding through WFI stalls by generating fake timer interrupts * ``+spike-debug``: Enables debug Spike logging * ``+spike-verbose``: Enables Spike commit-log generation + +Adding a new spike device model +------------------------------- + +Spike comes with a few functional device models such as UART, CLINT, and PLIC. +However, you may want to add custom device models into Spike such as a block device. +Example devices are in the ``toolchains/riscv-tools/riscv-spike-devices`` directory. +These devices are compiled as a shared library that can be dynamically linked to Spike. + +To compile these plugins, run ``make`` inside ``toolchains/riscv-tools/riscv-spike-devices``. This will generate a ``libspikedevices.so``. + +To hook up a block device to spike and provide a default image to initialize the block device, run + +.. code-block:: shell + + spike --extlib=libspikedevices.so --device="iceblk,img=" + +. + +The ``--device`` option consists of the device name and arguments. +In the above example ``iceblk`` is the device name and ``img=`` is the argument passed on to the plugin device. diff --git a/generators/chipyard/src/main/resources/csrc/spiketile.cc b/generators/chipyard/src/main/resources/csrc/spiketile.cc index 3b14079b..5483cf6b 100644 --- a/generators/chipyard/src/main/resources/csrc/spiketile.cc +++ b/generators/chipyard/src/main/resources/csrc/spiketile.cc @@ -447,18 +447,6 @@ chipyard_simif_t::chipyard_simif_t(size_t icache_ways, use_stq(false), htif(nullptr), fast_clint(false), - cfg(std::make_pair(0, 0), - nullptr, - isastr, - "MSU", - "vlen:128,elen:64", - false, - endianness_little, - pmpregions, - std::vector(), - std::vector(), - false, - 0), accessed_tofrom_host(false), icache_ways(icache_ways), icache_sets(icache_sets), @@ -470,6 +458,19 @@ chipyard_simif_t::chipyard_simif_t(size_t icache_ways, mmio_inflight(false) { + cfg.initrd_bounds = std::make_pair(0, 0); + cfg.bootargs = nullptr; + cfg.isa = isastr; + cfg.priv = "MSU"; + cfg.varch = "vlen:128,elen:64"; + cfg.misaligned = false; + cfg.endianness = endianness_little; + cfg.pmpregions = pmpregions; + cfg.mem_layout = std::vector(); + cfg.hartids = std::vector(); + cfg.explicit_hartids = false; + cfg.trigger_count = 0; + icache.resize(icache_ways); for (auto &w : icache) { w.resize(icache_sets); diff --git a/generators/testchipip b/generators/testchipip index c4c0774f..7e075b9c 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit c4c0774f5ff7a407dd81e5f0b4289a2fdd9e8d63 +Subproject commit 7e075b9cf63da626234dc22fda45ac9f1e82ffbc diff --git a/scripts/build-toolchain-extra.sh b/scripts/build-toolchain-extra.sh index cc69ae1d..28cc9dfa 100755 --- a/scripts/build-toolchain-extra.sh +++ b/scripts/build-toolchain-extra.sh @@ -125,4 +125,10 @@ cd generators/testchipip/uart_tsi make cp uart_tsi $RISCV/bin +echo '==> Installing spike-devices' +cd $RDIR +git submodule update --init toolchains/riscv-tools/riscv-spike-devices +cd toolchains/riscv-tools/riscv-spike-devices +make install + echo "Extra Toolchain Utilities/Tests Build Complete!" diff --git a/toolchains/riscv-tools/riscv-spike-devices b/toolchains/riscv-tools/riscv-spike-devices new file mode 160000 index 00000000..8b4836db --- /dev/null +++ b/toolchains/riscv-tools/riscv-spike-devices @@ -0,0 +1 @@ +Subproject commit 8b4836db0b5b4ed0a9bab34e7707fe40c7c014be