Fix forms of passes to happen before replseqmem

This ensures the conf file doesn't have any testharness
memories, which are too big and break downstream tools
This commit is contained in:
Colin Schmidt
2019-03-17 08:24:20 -07:00
committed by Colin Schmidt
parent 98a410812c
commit 6cdf978a6d
2 changed files with 4 additions and 4 deletions

View File

@@ -25,8 +25,8 @@ class ConvertToExtModPass(classify: (Module) => Boolean) extends Pass {
} }
} }
class ConvertToExtMod(classify: (Module) => Boolean) extends Transform with SeqTransformBased { class ConvertToExtMod(classify: (Module) => Boolean) extends Transform with SeqTransformBased {
def inputForm = MidForm def inputForm = HighForm
def outputForm = MidForm def outputForm = HighForm
def transforms = Seq(new ConvertToExtModPass(classify)) def transforms = Seq(new ConvertToExtModPass(classify))
def execute(state: CircuitState): CircuitState = { def execute(state: CircuitState): CircuitState = {

View File

@@ -11,8 +11,8 @@ import firrtl.transforms.DontTouchAnnotation
// Removes all the unused modules in a circuit by recursing through every // Removes all the unused modules in a circuit by recursing through every
// instance (starting at the main module) // instance (starting at the main module)
class RemoveUnusedModules extends Transform { class RemoveUnusedModules extends Transform {
def inputForm = MidForm def inputForm = HighForm
def outputForm = MidForm def outputForm = HighForm
def execute(state: CircuitState): CircuitState = { def execute(state: CircuitState): CircuitState = {
val modulesByName = state.circuit.modules.map{ val modulesByName = state.circuit.modules.map{