Fix forms of passes to happen before replseqmem
This ensures the conf file doesn't have any testharness memories, which are too big and break downstream tools
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committed by
Colin Schmidt
parent
98a410812c
commit
6cdf978a6d
@@ -25,8 +25,8 @@ class ConvertToExtModPass(classify: (Module) => Boolean) extends Pass {
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}
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}
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class ConvertToExtMod(classify: (Module) => Boolean) extends Transform with SeqTransformBased {
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def inputForm = MidForm
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def outputForm = MidForm
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def inputForm = HighForm
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def outputForm = HighForm
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def transforms = Seq(new ConvertToExtModPass(classify))
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def execute(state: CircuitState): CircuitState = {
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@@ -11,8 +11,8 @@ import firrtl.transforms.DontTouchAnnotation
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// Removes all the unused modules in a circuit by recursing through every
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// instance (starting at the main module)
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class RemoveUnusedModules extends Transform {
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def inputForm = MidForm
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def outputForm = MidForm
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def inputForm = HighForm
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def outputForm = HighForm
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def execute(state: CircuitState): CircuitState = {
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val modulesByName = state.circuit.modules.map{
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