Support Tilelink over serial

.circleci/config.yml

@@ -204,6 +204,11 @@ jobs:
         steps:
             - prepare-rtl:
                 project-key: "chipyard-dmirocket"
+    prepare-chipyard-tlserial:
+        executor: main-env
+        steps:
+            - prepare-rtl:
+                project-key: "chipyard-tlserial"
     prepare-chipyard-sha3:
         executor: main-env
         steps:
@@ -302,6 +307,11 @@ jobs:
         steps:
             - run-tests:
                 project-key: "chipyard-dmirocket"
+    chipyard-tlserial-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                project-key: "chipyard-tlserial"
     chipyard-sha3-run-tests:
         executor: main-env
         steps:
@@ -456,6 +466,11 @@ workflows:
                     - install-riscv-toolchain
                     - install-verilator
 
+            - prepare-chipyard-tlserial:
+                requires:
+                    - install-riscv-toolchain
+                    - install-verilator
+
             - prepare-chipyard-sha3:
                 requires:
                     - install-riscv-toolchain
@@ -551,6 +566,10 @@ workflows:
                 requires:
                     - prepare-chipyard-dmirocket
 
+            - chipyard-tlserial-run-tests:
+                requires:
+                    - prepare-chipyard-tlserial
+
             - chipyard-sha3-run-tests:
                 requires:
                     - prepare-chipyard-sha3

.circleci/defaults.sh

@@ -49,6 +49,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim
 declare -A mapping
 mapping["chipyard-rocket"]=""
 mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig"
+mapping["chipyard-tlserial"]=" CONFIG=TLSerialRocketConfig"
 mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig"
 mapping["chipyard-streaming-fir"]=" CONFIG=StreamingFIRRocketConfig"
 mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketConfig"

.circleci/run-tests.sh

@@ -35,6 +35,9 @@ case $1 in
     chipyard-dmirocket)
         run_bmark ${mapping[$1]}
         ;;
+    chipyard-tlserial)
+        run_bmark ${mapping[$1]}
+        ;;
     chipyard-boom)
         run_bmark ${mapping[$1]}
         ;;

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -16,7 +16,8 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
   with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
   with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
-  with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port
+  with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the tilelink-over-serial backing memory
+  with testchipip.CanHavePeripheryTSISerial // Enables optionally adding the TSI serial-adapter and port
   with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
   with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
   with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller

generators/chipyard/src/main/scala/HarnessBinders.scala

@@ -223,15 +223,15 @@ class WithTiedOffDebug extends OverrideHarnessBinder({
 })
 
 
-class WithTiedOffSerial extends OverrideHarnessBinder({
+class WithTiedOffTSISerial extends OverrideHarnessBinder({
-  (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
+  (system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
     ports.map { p => SerialAdapter.tieoff(Some(p.bits)) }
     Nil
   }
 })
 
-class WithSimSerial extends OverrideHarnessBinder({
+class WithSimTSISerial extends OverrideHarnessBinder({
-  (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
+  (system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
     ports.map { p =>
       val ser_success = SerialAdapter.connectSimSerial(p.bits, p.clock, th.harnessReset)
       when (ser_success) { th.success := true.B }
@@ -240,6 +240,34 @@ class WithSimSerial extends OverrideHarnessBinder({
   }
 })
 
+class WithSimTLSerial(withHarnessSerialAdapter: Boolean = false) extends OverrideHarnessBinder({
+  (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
+    implicit val p = chipyard.iobinders.GetSystemParameters(system)
+    ports.map({ port =>
+      withClockAndReset(port.clock, th.harnessReset) {
+        val lRam = LazyModule(new SerialRAM(
+          p(SerialTLKey).get.width,
+          p(SerialTLKey).get.memParams.master.size,
+          p(SerialTLKey).get.memParams.master.base,
+          managerEdge = system.serdesser.get.managerNode.edges.in(0),
+          clientEdge = system.serdesser.get.clientNode.edges.out(0)
+        ))
+        val ram = Module(lRam.module)
+        ram.io.ser <> port.bits
+
+        require(lRam.serdesser.module.mergedParams == system.serdesser.get.module.mergedParams,
+          "Mismatch between chip-side diplomatic params and testram diplomatic params")
+        if (withHarnessSerialAdapter) {
+          val success = SerialAdapter.connectSimSerial(Some(ram.io.tsi_ser), port.clock, th.harnessReset.asBool)
+          when (success) { th.success := true.B }
+        } else {
+          SerialAdapter.tieoff(Some(ram.io.tsi_ser))
+        }
+      }
+    })
+  }
+})
+
 class WithTraceGenSuccess extends OverrideHarnessBinder({
   (system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Bool]) => {
     ports.map { p => when (p) { th.success := true.B } }

generators/chipyard/src/main/scala/IOBinders.scala

@@ -250,11 +250,20 @@ class WithDebugIOCells extends OverrideIOBinder({
   }
 })
 
-class WithSerialIOCells extends OverrideIOBinder({
+class WithSerialTSIIOCells extends OverrideIOBinder({
-  (system: CanHavePeripherySerial) => system.serial.map({ s =>
+  (system: CanHavePeripheryTSISerial) => system.serial_tsi.map({ s =>
     val sys = system.asInstanceOf[BaseSubsystem]
-    val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, Some("serial"), sys.p(IOCellKey))
+    val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, Some("serial_tsi"), sys.p(IOCellKey))
-    port.suggestName("serial")
+    port.suggestName("serial_tsi")
+    (Seq(port), cells)
+  }).getOrElse((Nil, Nil))
+})
+
+class WithSerialTLIOCells extends OverrideIOBinder({
+  (system: CanHavePeripheryTLSerial) => system.serial_tl.map({ s =>
+    val sys = system.asInstanceOf[BaseSubsystem]
+    val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, Some("serial_tl"), sys.p(IOCellKey))
+    port.suggestName("serial_tl")
     (Seq(port), cells)
   }).getOrElse((Nil, Nil))
 })

generators/chipyard/src/main/scala/Subsystem.scala

@@ -25,12 +25,12 @@ import freechips.rocketchip.amba.axi4._
 import boom.common.{BoomTile}
 
 
-import testchipip.{DromajoHelper, CanHavePeripherySerial, SerialKey}
+import testchipip.{DromajoHelper, CanHavePeripheryTSISerial, SerialTSIKey}
 
 trait CanHaveHTIF { this: BaseSubsystem =>
   // Advertise HTIF if system can communicate with fesvr
   if (this match {
-    case _: CanHavePeripherySerial if p(SerialKey) => true
+    case _: CanHavePeripheryTSISerial if p(SerialTSIKey).nonEmpty => true
     case _: HasPeripheryDebug if p(ExportDebug).protocols.nonEmpty => true
     case _ => false
   }) {

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -15,7 +15,7 @@ class AbstractConfig extends Config(
   new chipyard.harness.WithUARTAdapter ++                       // add UART adapter to display UART on stdout, if uart is present
   new chipyard.harness.WithBlackBoxSimMem ++                    // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled
   new chipyard.harness.WithSimDebug ++                          // add SimJTAG or SimDTM adapters if debug module is enabled
-  new chipyard.harness.WithSimSerial ++                         // add SimSerial adapter for HTIF, if serial port is present
+  new chipyard.harness.WithSimTSISerial ++                      // add SimSerial adapter for HTIF, if serial port is present
   new chipyard.harness.WithGPIOTiedOff ++                       // tie-off chiptop GPIOs, if GPIOs are present
   new chipyard.harness.WithSimSPIFlashModel ++                  // add simulated SPI flash memory, if SPI is enabled
   new chipyard.harness.WithSimAXIMMIO ++                        // add SimAXIMem for axi4 mmio port, if enabled
@@ -29,7 +29,8 @@ class AbstractConfig extends Config(
   new chipyard.iobinders.WithL2FBusAXI4Punchthrough ++
   new chipyard.iobinders.WithBlockDeviceIOPunchthrough ++
   new chipyard.iobinders.WithNICIOPunchthrough ++
-  new chipyard.iobinders.WithSerialIOCells ++
+  new chipyard.iobinders.WithSerialTSIIOCells ++
+  new chipyard.iobinders.WithSerialTLIOCells ++
   new chipyard.iobinders.WithDebugIOCells ++
   new chipyard.iobinders.WithUARTIOCells ++
   new chipyard.iobinders.WithGPIOCells ++
@@ -39,7 +40,7 @@ class AbstractConfig extends Config(
   new chipyard.iobinders.WithExtInterruptIOCells ++
 
 
-  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
+  new testchipip.WithSerialTSI ++                                // use testchipip serial offchip link
   new chipyard.config.WithBootROM ++                             // use default bootrom
   new chipyard.config.WithUART ++                                // add a UART
   new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs

generators/chipyard/src/main/scala/config/ArianeConfigs.scala

@@ -13,7 +13,7 @@ class ArianeConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 class dmiArianeConfig extends Config(
-  new chipyard.harness.WithTiedOffSerial ++            // Tie off the serial port, override default instantiation of SimSerial
+  new chipyard.harness.WithTiedOffTSISerial ++         // Tie off the serial port, override default instantiation of SimSerial
   new chipyard.config.WithDMIDTM ++                    // have debug module expose a clocked DMI port
   new ariane.WithNArianeCores(1) ++                    // single Ariane core
   new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -25,7 +25,7 @@ class GemminiRocketConfig extends Config(
 
 // DOC include start: DmiRocket
 class dmiRocketConfig extends Config(
-  new chipyard.harness.WithTiedOffSerial ++                      // don't use serial to drive the chip, since we use DMI instead
+  new chipyard.harness.WithTiedOffTSISerial ++                      // don't use serial to drive the chip, since we use DMI instead
   new chipyard.config.WithDMIDTM ++                              // have debug module expose a clocked DMI port
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
@@ -182,4 +182,10 @@ class DividedClockRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
-
+class TLSerialRocketConfig extends Config(
+  new chipyard.harness.WithSimTLSerial(withHarnessSerialAdapter = true) ++ // add external TL backing memory, and external serial adapter
+  new testchipip.WithDefaultSerialTL ++                                    // support tilelink-over-serial
+  new testchipip.WithNoSerialTSI ++                                        // remove internal serial adapter
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.subsystem.WithNoMemPort ++                      // remove AXI4 backing memory
+  new chipyard.config.AbstractConfig)

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -56,7 +56,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
 })
 
 class WithSerialBridge extends OverrideHarnessBinder({
-  (system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
+  (system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
     ports.map { p =>
       withClockAndReset(p.clock, th.harnessReset) {
         SerialBridge(p.clock, p.bits, MainMemoryConsts.globalName)(GetSystemParameters(system))

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -84,7 +84,7 @@ class WithFireSimConfigTweaks extends Config(
   // Required: Adds IO to attach SerialBridge. The SerialBridges is responsible
   // for signalling simulation termination under simulation success. This fragment can
   // be removed if you supply an auxiliary bridge that signals simulation termination
-  new testchipip.WithTSI ++
+  new testchipip.WithSerialTSI ++
   // Optional: Removing this will require using an initramfs under linux
   new testchipip.WithBlockDevice ++
   // Required*: Scale default baud rate with periphery bus frequency
@@ -131,7 +131,7 @@ class FireSimSmallSystemConfig extends Config(
   new WithoutClockGating ++
   new WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
-  new testchipip.WithTSI ++
+  new testchipip.WithSerialTSI ++
   new testchipip.WithBlockDevice ++
   new chipyard.config.WithUART ++
   new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++