wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Support Tilelink over serial

Browse Source
This commit is contained in:
Jerry Zhao
2020-09-13 11:59:16 -07:00
parent be0c041232
commit 6c5bce5430
14 changed files with 90 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
generators/firechip/src/main/scala/BridgeBinders.scala
View File

@@ -56,7 +56,7 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
})
class WithSerialBridge extends OverrideHarnessBinder({
(system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
(system: CanHavePeripheryTSISerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
ports.map { p =>
withClockAndReset(p.clock, th.harnessReset) {
SerialBridge(p.clock, p.bits, MainMemoryConsts.globalName)(GetSystemParameters(system))

4
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -84,7 +84,7 @@ class WithFireSimConfigTweaks extends Config(
// Required: Adds IO to attach SerialBridge. The SerialBridges is responsible
// for signalling simulation termination under simulation success. This fragment can
// be removed if you supply an auxiliary bridge that signals simulation termination
new testchipip.WithTSI ++
new testchipip.WithSerialTSI ++
// Optional: Removing this will require using an initramfs under linux
new testchipip.WithBlockDevice ++
// Required*: Scale default baud rate with periphery bus frequency
@@ -131,7 +131,7 @@ class FireSimSmallSystemConfig extends Config(
new WithoutClockGating ++
new WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
new testchipip.WithTSI ++
new testchipip.WithSerialTSI ++
new testchipip.WithBlockDevice ++
new chipyard.config.WithUART ++
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++