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add verilator simulation

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Howard Mao
2016-10-25 11:38:00 -07:00
parent 9a09850dd2
commit 6c115b4234
4 changed files with 93 additions and 1 deletions
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5
verisim/.gitignore vendored Normal file
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@@ -0,0 +1,5 @@
simulator-*
generated-src/
verilator/
DVEfiles/
*.log