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[ci skip] Re-add suggestName for axi4 mmio mem

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This commit is contained in:
Jerry Zhao
2023-10-13 17:36:41 -07:00
committed by GitHub
parent deab3b11b6
commit 6bd2e9dddb
1 changed files with 1 additions and 1 deletions
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2
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
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@@ -135,7 +135,7 @@ class WithBlackBoxSimMem(additionalLatency: Int = 0) extends HarnessBinder({
class WithSimAXIMMIO extends HarnessBinder({ class WithSimAXIMMIO extends HarnessBinder({
case (th: HasHarnessInstantiators, port: AXI4MMIOPort) => { case (th: HasHarnessInstantiators, port: AXI4MMIOPort) => {
val mmio_mem = LazyModule(new SimAXIMem(port.edge, size = port.params.size)(Parameters.empty)) val mmio_mem = LazyModule(new SimAXIMem(port.edge, size = port.params.size)(Parameters.empty))
withClock(port.io.clock) { Module(mmio_mem.module) } withClock(port.io.clock) { Module(mmio_mem.module).suggestName("mmio_mem") }
mmio_mem.io_axi4.head <> port.io.bits mmio_mem.io_axi4.head <> port.io.bits
} }
}) })