diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala
index bee73b69..70fe38e7 100644
--- a/generators/chipyard/src/main/scala/Clocks.scala
+++ b/generators/chipyard/src/main/scala/Clocks.scala
@@ -5,12 +5,13 @@ import chisel3._
 import scala.collection.mutable.{ArrayBuffer}
 
 import freechips.rocketchip.prci._
-import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
+import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey, InstantiatesTiles}
 import freechips.rocketchip.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy.{OutwardNodeHandle, InModuleBody, LazyModule}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 
 import barstools.iocell.chisel._
+import testchipip.{TLTileResetCtrl}
 
 import chipyard.clocking._
 
@@ -109,9 +110,20 @@ object ClockingSchemeGenerators {
         l.asyncClockGroupsNode
     }
 
+    // Add a control register for each tile's reset
+    val resetSetter = chiptop.lazySystem match {
+      case sys: BaseSubsystem with InstantiatesTiles => TLTileResetCtrl(sys)
+      case _ => ClockGroupEphemeralNode()
+    }
+
     val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node
-    chiptop.implicitClockSinkNode := ClockGroup() := aggregator
-    systemAsyncClockGroup :*= ClockGroupNamePrefixer() :*= aggregator
+    (chiptop.implicitClockSinkNode
+      := ClockGroup()
+      := aggregator)
+    (systemAsyncClockGroup
+      :*= resetSetter
+      :*= ClockGroupNamePrefixer()
+      :*= aggregator)
 
     val referenceClockSource =  ClockSourceNode(Seq(ClockSourceParameters()))
     (aggregator
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index a056ec32..d413cc12 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -117,6 +117,7 @@ class LoopbackNICRocketConfig extends Config(
 
 // DOC include start: l1scratchpadrocket
 class ScratchpadOnlyRocketConfig extends Config(
+  new testchipip.WithSerialPBusMem ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++
diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala
index 8fa0b54e..760e89c3 100644
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -9,7 +9,7 @@ import freechips.rocketchip.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule}
 import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
 import freechips.rocketchip.amba.axi4.{AXI4Bundle}
-import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp}
+import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp, ExtMem}
 import freechips.rocketchip.tile.{RocketTile}
 import sifive.blocks.devices.uart._
 
@@ -67,9 +67,10 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
 
 class WithSerialBridge extends OverrideHarnessBinder({
   (system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
-    ports.map { p =>
-      val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, p, th.harnessReset)
-      SerialBridge(p.clock, ram.module.io.tsi_ser, MainMemoryConsts.globalName)(GetSystemParameters(system))
+    ports.map { port =>
+      implicit val p = GetSystemParameters(system)
+      val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset)
+      SerialBridge(port.clock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName))
     }
     Nil
   }
diff --git a/generators/testchipip b/generators/testchipip
index 51240a9a..03af7aa5 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 51240a9a892e871a20f3038ea6bc4293318d73db
+Subproject commit 03af7aa53988dd96dffd613d1d50a5c6661e0a82
diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala
index b2982db7..f40ad032 100644
--- a/generators/utilities/src/main/scala/Simulator.scala
+++ b/generators/utilities/src/main/scala/Simulator.scala
@@ -83,6 +83,8 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
   }
   def resources(sim: Simulator): Seq[String] = Seq(
     "/testchipip/csrc/SimSerial.cc",
+    "/testchipip/csrc/testchip_tsi.cc",
+    "/testchipip/csrc/testchip_tsi.h",
     "/testchipip/csrc/SimDRAM.cc",
     "/testchipip/csrc/mm.h",
     "/testchipip/csrc/mm.cc",
diff --git a/sims/firesim b/sims/firesim
index 64b55aff..a8900919 160000
--- a/sims/firesim
+++ b/sims/firesim
@@ -1 +1 @@
-Subproject commit 64b55aff3997d4cee4494eef72c2f1a15b3002b2
+Subproject commit a8900919cbc826e8e1610805c4229e31a849ad3c
diff --git a/software/firemarshal b/software/firemarshal
index 83b86610..45aebace 160000
--- a/software/firemarshal
+++ b/software/firemarshal
@@ -1 +1 @@
-Subproject commit 83b866104c6860b5d03989a6cf8439aa6934b398
+Subproject commit 45aebace86d3a46c357337a19d4c8e894a5d0ed4