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Update FireSim to support harness clocks | Small config renaming

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This commit is contained in:
Abraham Gonzalez
2021-03-08 22:03:07 +00:00
parent 562d8e5116
commit 6ab8f8f8fc
6 changed files with 149 additions and 48 deletions
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2
generators/chipyard/src/main/scala/TestHarness.scala
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@@ -95,7 +95,7 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign
case d: HasReferenceClockFreq => d.refClockFreqMHz.getOrElse(p(DefaultClockFrequencyKey))
case _ => p(DefaultClockFrequencyKey)
}
val refClkBundle = p(HarnessClockInstantiatorKey).getClockBundleWire("chiptop_reference_clock", freqMHz * (1000 * 1000))
val refClkBundle = p(HarnessClockInstantiatorKey).getClockBundleWire("buildtop_reference_clock", freqMHz * (1000 * 1000))
harnessClock := refClkBundle.clock
harnessReset := WireInit(refClkBundle.reset)

1
generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
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@@ -89,6 +89,7 @@ class SimplePllConfiguration(
ElaborationArtefacts.add(s"${name}.freq-summary", summaryString)
println(summaryString)
}
def referenceSinkParams(): ClockSinkParameters = sinkDividerMap.find(_._2 == 1).get._1
}
case class DividerOnlyClockGeneratorNode(pllName: String)(implicit valName: ValName)