Add TSI Host Widget
This commit is contained in:
abejgonzalez
@@ -4,10 +4,16 @@ import chisel3._
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import chisel3.experimental.{attach}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.config.{Parameters, Field}
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import freechips.rocketchip.tilelink.{TLInwardNode}
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import sifive.fpgashells.shell._
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import sifive.fpgashells.ip.xilinx._
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import sifive.fpgashells.shell.xilinx._
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import sifive.fpgashells.clocks._
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import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG}
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import testchipip.{TSIHostParams, TSIHostWidgetIO}
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import chipyard.fpga.vcu118.{FMCPMap}
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@@ -144,58 +150,150 @@ class BringupGPIOVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInp
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def place(designInput: GPIODesignInput) = new BringupGPIOVCU118PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames)
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}
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//case class TSIShellInput()
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//case class TSIDesignInput(
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//
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// )(
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// implicit val p: Parameters)extends DDRDesignInput
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//
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//abstract class TSIOverlay(val params: TSIOverlayParams)
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// extends IOOverlay[TLTSIWithDDRIO, TLTSIHostWidget]
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//{
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// implicit val p = params.p
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//
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// // instantiate the tsi host widget and setup necessary connections
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// val (tlTsiHost, tlTsiMemNode) = TLTSIHostWidget.attach(TSIHostWidgetAttachParams(params.tsiHostParams, params.controlBus))
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// val tlTsiHostIONodeSink = tlTsiHost.ioNode.makeSink
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//
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// // instantiate the DDR
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// val size = p(TSIMigDDRSize)
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// val migParams = XilinxVCU118MIGParams(address = AddressSet.misaligned(params.tsiHostParams.targetBaseAddress, size))
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// val mig = LazyModule(new XilinxVCU118MIG(migParams))
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// val tsiIONode = BundleBridgeSource(() => new TSIHostWidgetIO(params.tsiHostParams.serialIfWidth))
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// val topTSIIONode = shell { tsiIONode.makeSink() }
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// val ddrIONode = BundleBridgeSource(() => mig.module.io.cloneType)
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// val topDDRIONode = shell { ddrIONode.makeSink() }
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// val ddrUI = shell { ClockSourceNode(freqMHz = 200) }
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// val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) }
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// areset := params.ddrParams.wrangler := ddrUI
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// val asyncSink = LazyModule(new TLAsyncCrossingSink)
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// val migClockReset = BundleBridgeSource(() => new Bundle {
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// val clock = Output(Clock())
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// val reset = Output(Bool())
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// })
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// val migClockResetTop = shell { migClockReset.makeSink() }
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//
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// // connect them
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// (mig.node := TLFragmenter(32,64,holdFirstDeny=true) := TLCacheCork() := TLSinkSetter(1 << 1) := TLSourceShrinker(1 << 4) := tlTsiMemNode)
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//
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// def designOutput = tlTsiHost
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// def ioFactory = new TLTSIWithDDRIO(params.tsiHostParams.serialIfWidth, size) // top level io of the shell
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//
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// InModuleBody {
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// val (t, _) = tsiIONode.out(0)
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// val tsi = tlTsiHostIONodeSink.bundle
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// tsi.serial_clock := t.serial_clock
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// tsi.serial.in.bits := t.serial.in.bits
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// tsi.serial.in.valid := t.serial.in.valid
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// tsi.serial.out.ready := t.serial.out.ready
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// t.serial.out.bits := tsi.serial.out.bits
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// t.serial.out.valid := tsi.serial.out.valid
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// t.serial.in.ready := tsi.serial.in.ready
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// ddrIONode.bundle <> mig.module.io
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// asyncSink.module.clock := migClockReset.bundle.clock
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// asyncSink.module.reset := migClockReset.bundle.reset
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// }
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//}
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//
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case class TSIHostShellInput()
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case class TSIHostDesignInput(
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wrangler: ClockAdapterNode,
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corePLL: PLLNode,
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tsiHostParams: TSIHostParams,
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node: BundleBridgeSource[TSIHostWidgetIO],
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vc7074gbdimm: Boolean = false
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)(
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implicit val p: Parameters)
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case class TSIHostOverlayOutput(ddr: TLInwardNode)
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trait TSIHostShellPlacer[Shell] extends ShellPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput]
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class TSIHostWithDDRIO(val w: Int, val size: BigInt) extends Bundle {
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val tsi = new TSIHostWidgetIO(w)
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val ddr = new XilinxVCU118MIGPads(size)
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}
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case object TSIHostOverlayKey extends Field[Seq[DesignPlacer[TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput]]](Nil)
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abstract class TSIHostPlacedOverlay[IO <: Data](val name: String, val di: TSIHostDesignInput, val si: TSIHostShellInput)
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extends IOPlacedOverlay[IO, TSIHostDesignInput, TSIHostShellInput, TSIHostOverlayOutput]
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{
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implicit val p = di.p
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}
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case object TSIHostVCU118DDRSize extends Field[BigInt](0x40000000L * 2) // 2GB
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class TSIHostVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: TSIHostDesignInput, val shellInput: TSIHostShellInput)
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extends TSIHostPlacedOverlay[TSIHostWithDDRIO](name, designInput, shellInput)
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{
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val size = p(TSIHostVCU118DDRSize)
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// connect the DDR
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val migParams = XilinxVCU118MIGParams(address = AddressSet.misaligned(di.tsiHostParams.targetBaseAddress, size))
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val mig = LazyModule(new XilinxVCU118MIG(migParams))
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val ioNode = BundleBridgeSource(() => mig.module.io.cloneType)
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val topIONode = shell { ioNode.makeSink() }
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val ddrUI = shell { ClockSourceNode(freqMHz = 200) }
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val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) }
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areset := designInput.wrangler := ddrUI
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// connect the TSI serial
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val tlTsiSerialSink = di.node.makeSink()
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val tsiIoNode = BundleBridgeSource(() => new TSIHostWidgetIO(di.tsiHostParams.serialIfWidth))
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val topTSIIONode = shell { tsiIoNode.makeSink() }
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def overlayOutput = TSIHostOverlayOutput(ddr = mig.node)
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def ioFactory = new TSIHostWithDDRIO(di.tsiHostParams.serialIfWidth, size)
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InModuleBody {
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// connect MIG
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ioNode.bundle <> mig.module.io
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// connect TSI serial
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val tsiSourcePort = tsiIoNode.bundle
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val tsiSinkPort = tlTsiSerialSink.bundle
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tsiSinkPort.serial_clock := tsiSourcePort.serial_clock
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tsiSourcePort.serial.out.bits := tsiSinkPort.serial.out.bits
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tsiSourcePort.serial.out.valid := tsiSinkPort.serial.out.valid
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tsiSinkPort.serial.out.ready := tsiSourcePort.serial.out.ready
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tsiSinkPort.serial.in.bits := tsiSourcePort.serial.in.bits
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tsiSinkPort.serial.in.valid := tsiSourcePort.serial.in.valid
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tsiSourcePort.serial.in.ready := tsiSinkPort.serial.in.ready
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}
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// connect the DDR port
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shell { InModuleBody {
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require (shell.sys_clock.get.isDefined, "Use of DDRVCU118Overlay depends on SysClockVCU118Overlay")
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val (sys, _) = shell.sys_clock.get.get.overlayOutput.node.out(0)
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val (ui, _) = ddrUI.out(0)
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val (ar, _) = areset.in(0)
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val ddrPort = topIONode.bundle.port
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io.ddr <> ddrPort
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ui.clock := ddrPort.c0_ddr4_ui_clk
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ui.reset := /*!ddrPort.mmcm_locked ||*/ ddrPort.c0_ddr4_ui_clk_sync_rst
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ddrPort.c0_sys_clk_i := sys.clock.asUInt
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ddrPort.sys_rst := sys.reset // pllReset
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ddrPort.c0_ddr4_aresetn := !ar.reset
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// This was just copied from the SiFive example, but it's hard to follow.
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// The pins are emitted in the following order:
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// adr[0->13], we_n, cas_n, ras_n, bg, ba[0->1], reset_n, act_n, ck_c, ck_t, cke, cs_n, odt, dq[0->63], dqs_c[0->7], dqs_t[0->7], dm_dbi_n[0->7]
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val allddrpins = Seq(
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"AM27", "AL27", "AP26", "AP25", "AN28", "AM28", "AP28", "AP27", "AN26", "AM26", "AR28", "AR27", "AV25", "AT25", // adr[0->13]
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"AV28", "AU26", "AV26", "AU27", // we_n, cas_n, ras_n, bg
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"AR25", "AU28", // ba[0->1]
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"BD35", "AN25", "AT27", "AT26", "AW28", "AY29", "BB29", // reset_n, act_n, ck_c, ck_t, cke, cs_n, odt
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"BD30", "BE30", "BD32", "BE33", "BC33", "BD33", "BC31", "BD31", "BA32", "BB33", "BA30", "BA31", "AW31", "AW32", "AY32", "AY33", // dq[0->15]
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"AV30", "AW30", "AU33", "AU34", "AT31", "AU32", "AU31", "AV31", "AR33", "AT34", "AT29", "AT30", "AP30", "AR30", "AN30", "AN31", // dq[16->31]
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"BE34", "BF34", "BC35", "BC36", "BD36", "BE37", "BF36", "BF37", "BD37", "BE38", "BC39", "BD40", "BB38", "BB39", "BC38", "BD38", // dq[32->47]
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"BB36", "BB37", "BA39", "BA40", "AW40", "AY40", "AY38", "AY39", "AW35", "AW36", "AU40", "AV40", "AU38", "AU39", "AV38", "AV39", // dq[48->63]
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"BF31", "BA34", "AV29", "AP32", "BF35", "BF39", "BA36", "AW38", // dqs_c[0->7]
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"BF30", "AY34", "AU29", "AP31", "BE35", "BE39", "BA35", "AW37", // dqs_t[0->7]
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"BE32", "BB31", "AV33", "AR32", "BC34", "BE40", "AY37", "AV35") // dm_dbi_n[0->7]
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(IOPin.of(io) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) }
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} }
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shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.c0_ddr4_ui_clk))
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}
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class BringupTSIHostVCU118PlacedOverlay(override val shell: VCU118ShellBasicOverlays, override val name: String, override val designInput: TSIHostDesignInput, override val shellInput: TSIHostShellInput)
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extends TSIHostVCU118PlacedOverlay(shell, name, designInput, shellInput)
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{
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// connect the TSI port
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shell { InModuleBody {
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// connect TSI signals
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val tsiPort = topTSIIONode.bundle
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io.tsi <> tsiPort
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require(di.tsiHostParams.serialIfWidth == 4)
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val clkIo = IOPin(io.tsi.serial_clock)
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val packagePinsWithPackageIOs = Seq(
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(FMCPMap("D8"), clkIo),
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(FMCPMap("D17"), IOPin(io.tsi.serial.out.ready)),
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(FMCPMap("D18"), IOPin(io.tsi.serial.out.valid)),
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(FMCPMap("D11"), IOPin(io.tsi.serial.out.bits, 0)),
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(FMCPMap("D12"), IOPin(io.tsi.serial.out.bits, 1)),
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(FMCPMap("D14"), IOPin(io.tsi.serial.out.bits, 2)),
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(FMCPMap("D15"), IOPin(io.tsi.serial.out.bits, 3)),
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(FMCPMap("D26"), IOPin(io.tsi.serial.in.ready)),
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(FMCPMap("D27"), IOPin(io.tsi.serial.in.valid)),
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(FMCPMap("D20"), IOPin(io.tsi.serial.in.bits, 0)),
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(FMCPMap("D21"), IOPin(io.tsi.serial.in.bits, 1)),
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(FMCPMap("D23"), IOPin(io.tsi.serial.in.bits, 2)),
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(FMCPMap("D24"), IOPin(io.tsi.serial.in.bits, 3)))
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packagePinsWithPackageIOs foreach { case (pin, io) => {
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shell.xdc.addPackagePin(io, pin)
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shell.xdc.addIOStandard(io, "LVCMOS18")
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} }
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// Don't add an IOB to the clock
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(packagePinsWithPackageIOs take 1) foreach { case (pin, io) => {
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shell.xdc.addIOB(io)
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} }
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shell.sdc.addClock("TSI_CLK", clkIo, 50)
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shell.sdc.addGroup(pins = Seq(clkIo))
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shell.xdc.clockDedicatedRouteFalse(clkIo)
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} }
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}
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class BringupTSIHostVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: TSIHostShellInput)(implicit val valName: ValName)
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extends TSIHostShellPlacer[VCU118ShellBasicOverlays] {
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def place(designInput: TSIHostDesignInput) = new BringupTSIHostVCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
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}
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