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Use harness binder chipId to support multi-chip id pins

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This commit is contained in:
Ella Schwarz
2024-01-12 11:39:54 -08:00
parent 8a4fc7c82f
commit 67faf0c3e3
2 changed files with 3 additions and 2 deletions
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1
generators/chipyard/src/main/scala/config/ChipletConfigs.scala
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@@ -11,6 +11,7 @@ import testchipip.soc.{OBUS}
// Simple design which exposes a second serial-tl port that can connect to another instance of itself // Simple design which exposes a second serial-tl port that can connect to another instance of itself
class SymmetricChipletRocketConfig extends Config( class SymmetricChipletRocketConfig extends Config(
new testchipip.soc.WithChipIdPin ++ // Add pin to identify chips
new chipyard.harness.WithSerialTLTiedOff(tieoffs=Some(Seq(1))) ++ // Tie-off the chip-to-chip link in single-chip sims new chipyard.harness.WithSerialTLTiedOff(tieoffs=Some(Seq(1))) ++ // Tie-off the chip-to-chip link in single-chip sims
new testchipip.serdes.WithSerialTL(Seq( new testchipip.serdes.WithSerialTL(Seq(
testchipip.serdes.SerialTLParams( // 0th serial-tl is chip-to-bringup-fpga testchipip.serdes.SerialTLParams( // 0th serial-tl is chip-to-bringup-fpga

4
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
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@@ -254,8 +254,8 @@ class WithSimTSIOverSerialTL extends HarnessBinder({
//TODO: Set with chipId argument to harness binder, hardcoding is temporary hack //TODO: Set with chipId argument to harness binder, hardcoding is temporary hack
class WithDriveChipIdPin extends HarnessBinder({ class WithDriveChipIdPin extends HarnessBinder({
case (th: HasHarnessInstantiators, port: ChipIdPort) => { case (th: HasHarnessInstantiators, port: ChipIdPort, chipId: Int) => {
port.io := 0.U port.io := chipId.U
} }
}) })