Refactor tapeout for Chisel 3.4, Firrtl 1.4

- Remove clk package based on discussion with Colin
- Annotations need to be refactored to using latest API
  - Generally that involves making annos generated by a anonymous ChiselAnnotation
  - The chisel annotations will use RunFirrtlTransform to queue up its associated transform
  - Chisel annotation provieds toFirrtl to generate Firrtl form of annotation
- Usages of unapply on firrtl annotations cannot use generic unapply(target, transform, data) which has been eliminated
- Have transforms use with DependencyAPIMigration to avoid deprecated `form`s
- Added some 'see License comments
- TechnologyLocation section of AddIOPadsSpec does not currently run because there is no content for it.
  - Added some tests for annotation serialization here

tapeout/src/test/scala/transforms/ResetInverterSpec.scala

@@ -3,7 +3,7 @@
 package barstools.tapeout.transforms
 
 import chisel3._
-import firrtl._
+import chisel3.stage.ChiselStage
 import org.scalatest.{FreeSpec, Matchers}
 
 class ExampleModuleNeedsResetInverted extends Module with ResetInverter {
@@ -19,22 +19,15 @@ class ExampleModuleNeedsResetInverted extends Module with ResetInverter {
 }
 
 class ResetNSpec extends FreeSpec with Matchers {
-
   "Inverting reset needs to be done throughout module" in {
-    val optionsManager = new ExecutionOptionsManager("dsptools") with HasChiselExecutionOptions with HasFirrtlOptions {
-      firrtlOptions = firrtlOptions.copy(compilerName = "low", customTransforms = List(new ResetInverterTransform)),
-    }
-    chisel3.Driver.execute(optionsManager, () => new ExampleModuleNeedsResetInverted) match {
-      case ChiselExecutionSuccess(_, chirrtl, Some(FirrtlExecutionSuccess(_, firrtl))) =>
-        chirrtl should include ("input reset :")
-        chirrtl should not include "input reset_n :"
-        chirrtl should not include "node reset = not(reset_n)"
+    val chirrtl = (new ChiselStage).emitChirrtl(new ExampleModuleNeedsResetInverted, Array())
+    chirrtl should include("input reset :")
+    (chirrtl should not).include("input reset_n :")
+    (chirrtl should not).include("node reset = not(reset_n)")
 
-        firrtl should include ("input reset_n :")
-        firrtl should include ("node reset = not(reset_n)")
-        firrtl should not include "input reset :"
-      case _ =>
-        // bad
-    }
+    val firrtl = (new ChiselStage).emitFirrtl(new ExampleModuleNeedsResetInverted, Array("-X", "low"))
+    firrtl should include("input reset_n :")
+    firrtl should include("node reset = not(reset_n)")
+    (firrtl should not).include("input reset :")
   }
 }