Merge pull request #1710 from ucb-bar/organize_tcip

Update testchipip imports with new testchipip organization

docs/Customization/Memory-Hierarchy.rst

@@ -94,7 +94,7 @@ memory channel.
 
 Instead of connecting to off-chip DRAM, you can instead connect a scratchpad
 and remove the off-chip link. This is done by adding a fragment like
-``testchipip.WithScratchpad`` to your configuration and removing the
+``testchipip.soc.WithScratchpad`` to your configuration and removing the
 memory port with ``freechips.rocketchip.subsystem.WithNoMemPort``.
 
 .. literalinclude:: ../../generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala

fpga/src/main/scala/arty/Configs.scala

@@ -11,7 +11,7 @@ import freechips.rocketchip.tile._
 
 import sifive.blocks.devices.uart._
 
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
 
 import chipyard.{BuildSystem}
 
@@ -30,7 +30,7 @@ class WithArtyTweaks extends Config(
   new chipyard.config.WithFrontBusFrequency(32) ++
   new chipyard.config.WithControlBusFrequency(32) ++
   new chipyard.config.WithPeripheryBusFrequency(32) ++
-  new testchipip.WithNoSerialTL
+  new testchipip.serdes.WithNoSerialTL
 )
 
 class TinyRocketArtyConfig extends Config(

fpga/src/main/scala/arty100t/Configs.scala

@@ -12,7 +12,7 @@ import freechips.rocketchip.tile._
 import sifive.blocks.devices.uart._
 import sifive.fpgashells.shell.{DesignKey}
 
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
 
 import chipyard.{BuildSystem}
 
@@ -25,7 +25,7 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
   new WithArty100TUARTTSI ++
   new WithArty100TDDRTL ++
   new WithNoDesignKey ++
-  new testchipip.WithUARTTSIClient ++
+  new testchipip.tsi.WithUARTTSIClient ++
   new chipyard.harness.WithSerialTLTiedOff ++
   new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++
   new chipyard.config.WithMemoryBusFrequency(freqMHz) ++
@@ -56,5 +56,5 @@ class NoCoresArty100TConfig extends Config(
 class BringupArty100TConfig extends Config(
   new WithArty100TSerialTLToGPIO ++
   new WithArty100TTweaks(freqMHz = 50) ++
-  new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
+  new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
   new chipyard.ChipBringupHostConfig)

fpga/src/main/scala/arty100t/HarnessBinders.scala

@@ -20,8 +20,6 @@ import chipyard._
 import chipyard.harness._
 import chipyard.iobinders._
 
-import testchipip._
-
 class WithArty100TUARTTSI extends HarnessBinder({
   case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
     val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]

fpga/src/main/scala/nexysvideo/Configs.scala

@@ -12,7 +12,7 @@ import freechips.rocketchip.tile._
 import sifive.blocks.devices.uart._
 import sifive.fpgashells.shell.{DesignKey}
 
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
 
 import chipyard.{BuildSystem}
 
@@ -26,7 +26,7 @@ class WithNexysVideoTweaks extends Config(
   new WithNexysVideoUARTTSI ++
   new WithNexysVideoDDRTL ++
   new WithNoDesignKey ++
-  new testchipip.WithUARTTSIClient ++
+  new testchipip.tsi.WithUARTTSIClient ++
   new chipyard.harness.WithSerialTLTiedOff ++
   new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
   new chipyard.config.WithMemoryBusFrequency(50.0) ++
@@ -53,7 +53,7 @@ class WithTinyNexysVideoTweaks extends Config(
   new WithNexysVideoUARTTSI ++
   new WithNoDesignKey ++
   new sifive.fpgashells.shell.xilinx.WithNoNexysVideoShellDDR ++ // no DDR
-  new testchipip.WithUARTTSIClient ++
+  new testchipip.tsi.WithUARTTSIClient ++
   new chipyard.harness.WithSerialTLTiedOff ++
   new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
   new chipyard.config.WithMemoryBusFrequency(50.0) ++

fpga/src/main/scala/nexysvideo/HarnessBinders.scala

@@ -12,8 +12,6 @@ import sifive.blocks.devices.uart.{UARTParams}
 
 import chipyard._
 import chipyard.harness._
-
-import testchipip._
 import chipyard.iobinders._
 
 class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({

fpga/src/main/scala/vc707/Configs.scala

@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import sifive.fpgashells.shell.{DesignKey}
 import sifive.fpgashells.shell.xilinx.{VC7074GDDRSize}
 
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
 
 import chipyard.{BuildSystem, ExtTLMem}
 import chipyard.harness._

fpga/src/main/scala/vcu118/Configs.scala

@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import sifive.fpgashells.shell.{DesignKey}
 import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
 
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
 
 import chipyard._
 import chipyard.harness._

fpga/src/main/scala/vcu118/bringup/Configs.scala

@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import sifive.fpgashells.shell.{DesignKey}
 import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
 
-import testchipip.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
+import testchipip.tsi.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
 
 import chipyard.{BuildSystem}
 

fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala

@@ -13,7 +13,7 @@ import sifive.fpgashells.shell.xilinx._
 import sifive.fpgashells.clocks._
 import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG}
 
-import testchipip.{TSIHostWidgetIO}
+import testchipip.tsi.{TSIHostWidgetIO}
 
 import chipyard.fpga.vcu118.{FMCPMap}
 

fpga/src/main/scala/vcu118/bringup/DigitalTop.scala

@@ -17,7 +17,7 @@ import chipyard.{DigitalTop, DigitalTopModule}
 
 class BringupVCU118DigitalTop(implicit p: Parameters) extends DigitalTop
   with sifive.blocks.devices.i2c.HasPeripheryI2C
-  with testchipip.HasPeripheryTSIHostWidget
+  with testchipip.tsi.HasPeripheryTSIHostWidget
 {
   override lazy val module = new BringupVCU118DigitalTopModule(this)
 }

fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala

@@ -11,7 +11,7 @@ import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
 import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort}
 import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO}
 
-import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
+import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
 
 import chipyard.harness._
 import chipyard.iobinders._

fpga/src/main/scala/vcu118/bringup/IOBinders.scala

@@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.{TLBundle}
 import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
 import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp}
 
-import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
+import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
 
 import chipyard.iobinders.{OverrideIOBinder, Port, TLMemPort}
 

fpga/src/main/scala/vcu118/bringup/TestHarness.scala

@@ -16,7 +16,8 @@ import sifive.blocks.devices.spi._
 import sifive.blocks.devices.i2c._
 import sifive.blocks.devices.gpio._
 
-import testchipip.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO, TLSinkSetter}
+import testchipip.tsi.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO}
+import testchipip.util.{TLSinkSetter}
 
 import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer}
 

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -13,13 +13,13 @@ import freechips.rocketchip.devices.tilelink._
 
 // DOC include start: DigitalTop
 class DigitalTop(implicit p: Parameters) extends ChipyardSystem
-  with testchipip.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport
+  with testchipip.tsi.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport
-  with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
+  with testchipip.boot.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
-  with testchipip.CanHavePeripheryBootAddrReg // Use programmable boot address register
+  with testchipip.boot.CanHavePeripheryBootAddrReg // Use programmable boot address register
-  with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
+  with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO
-  with testchipip.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad
+  with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad
-  with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
+  with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device
-  with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
+  with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
   with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C
   with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM
   with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
@@ -40,7 +40,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
 }
 
 class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
-  with testchipip.CanHaveTraceIOModuleImp
+  with testchipip.cosim.CanHaveTraceIOModuleImp
   with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
   with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
   with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp

generators/chipyard/src/main/scala/Subsystem.scala

@@ -24,7 +24,7 @@ import freechips.rocketchip.amba.axi4._
 import boom.common.{BoomTile}
 
 
-import testchipip.{CanHavePeripheryTLSerial, SerialTLKey}
+import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
 
 trait CanHaveHTIF { this: BaseSubsystem =>
   // Advertise HTIF if system can communicate with fesvr

generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala

@@ -14,7 +14,8 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.prci._
 
-import testchipip.{TLTileResetCtrl, ClockGroupFakeResetSynchronizer}
+import testchipip.boot.{TLTileResetCtrl}
+import testchipip.clocking.{ClockGroupFakeResetSynchronizer}
 
 case class ChipyardPRCIControlParams(
   slaveWhere: TLBusWrapperLocation = CBUS,

generators/chipyard/src/main/scala/clocking/TLClockDivider.scala

@@ -11,7 +11,7 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.util.ElaborationArtefacts
 
-import testchipip._
+import testchipip.clocking._
 
 // This module adds a TileLink memory-mapped clock divider to the clock graph
 // The output clock/reset pairs from this module should be synchronized later
@@ -38,7 +38,7 @@ class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit
       val reg = Module(new AsyncResetRegVec(w=divBits, init=0))
 
       println(s"${(address+i*4).toString(16)}: Clock domain $sinkName divider")
-      val divider = Module(new testchipip.ClockDivideOrPass(divBits, depth = 3, genClockGate = p(ClockGateImpl)))
+      val divider = Module(new ClockDivideOrPass(divBits, depth = 3, genClockGate = p(ClockGateImpl)))
       divider.io.clockIn := sources(i).clock
       // busReset is expected to be high for a long time, since reset will take a while to propagate
       // to the TL bus. While reset is propagating, make sure we propagate a fast, undivided clock

generators/chipyard/src/main/scala/clocking/TLClockSelector.scala

@@ -11,7 +11,7 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.util.ElaborationArtefacts
 
-import testchipip._
+import testchipip.clocking._
 
 case class ClockSelNode()(implicit valName: ValName)
   extends MixedNexusNode(ClockImp, ClockGroupImp)(
@@ -40,7 +40,7 @@ class TLClockSelector(address: BigInt, beatBytes: Int)(implicit p: Parameters) e
       sel := reg.io.q
       println(s"${(address+i*4).toString(16)}: Clock domain $sinkName clock mux")
 
-      val mux = testchipip.ClockMutexMux(clocks).suggestName(s"${sinkName}_clkmux")
+      val mux = ClockMutexMux(clocks).suggestName(s"${sinkName}_clkmux")
       mux.io.sel        := sel
       mux.io.resetAsync := asyncReset.asAsyncReset
       sinks(i).clock := mux.io.clockOut

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -61,12 +61,14 @@ class AbstractConfig extends Config(
   new chipyard.config.WithFrontBusFrequency(500.0) ++               // Default 500 MHz fbus
   new chipyard.config.WithOffchipBusFrequency(500.0) ++             // Default 500 MHz obus
 
-  new testchipip.WithCustomBootPin ++                               // add a custom-boot-pin to support pin-driven boot address
+  new testchipip.boot.WithCustomBootPin ++                          // add a custom-boot-pin to support pin-driven boot address
-  new testchipip.WithBootAddrReg ++                                 // add a boot-addr-reg for configurable boot address
+  new testchipip.boot.WithBootAddrReg ++                            // add a boot-addr-reg for configurable boot address
-  new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams(        // add a serial-tilelink interface
+  new testchipip.serdes.WithSerialTL(Seq(                           // add a serial-tilelink interface
-    client = Some(testchipip.SerialTLClientParams(idBits = 4)),     // serial-tilelink interface will master the FBUS, and support 4 idBits
+    testchipip.serdes.SerialTLParams(
-    width = 32                                                      // serial-tilelink interface with 32 lanes
+      client = Some(testchipip.serdes.SerialTLClientParams(idBits=4)), // serial-tilelink interface will master the FBUS, and support 4 idBits
-  ))) ++
+      width = 32                                                    // serial-tilelink interface with 32 lanes
+    )
+  )) ++
   new chipyard.config.WithDebugModuleAbstractDataWords(8) ++        // increase debug module data capacity
   new chipyard.config.WithBootROM ++                                // use default bootrom
   new chipyard.config.WithUART ++                                   // add a UART

generators/chipyard/src/main/scala/config/ChipConfigs.scala

@@ -3,7 +3,7 @@ package chipyard
 import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.subsystem.{MBUS, SBUS}
-import testchipip.{OBUS}
+import testchipip.soc.{OBUS}
 
 // A simple config demonstrating how to set up a basic chip in Chipyard
 class ChipLikeRocketConfig extends Config(
@@ -22,16 +22,16 @@ class ChipLikeRocketConfig extends Config(
   //==================================
   // Set up I/O
   //==================================
-  new testchipip.WithSerialTLWidth(4) ++                                                // 4bit wide Serialized TL interface to minimize IO
+  new testchipip.serdes.WithSerialTLWidth(4) ++                                         // 4bit wide Serialized TL interface to minimize IO
-  new testchipip.WithSerialTLMem(size = (1 << 30) * 4L) ++                              // Configure the off-chip memory accessible over serial-tl as backing memory
+  new testchipip.serdes.WithSerialTLMem(size = (1 << 30) * 4L) ++                       // Configure the off-chip memory accessible over serial-tl as backing memory
   new freechips.rocketchip.subsystem.WithNoMemPort ++                                   // Remove axi4 mem port
   new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++                          // 1 memory channel
 
   //==================================
   // Set up buses
   //==================================
-  new testchipip.WithOffchipBusClient(MBUS) ++                                          // offchip bus connects to MBUS, since the serial-tl needs to provide backing memory
+  new testchipip.soc.WithOffchipBusClient(MBUS) ++                                      // offchip bus connects to MBUS, since the serial-tl needs to provide backing memory
-  new testchipip.WithOffchipBus ++                                                      // attach a offchip bus, since the serial-tl will master some external tilelink memory
+  new testchipip.soc.WithOffchipBus ++                                                  // attach a offchip bus, since the serial-tl will master some external tilelink memory
 
   //==================================
   // Set up clock./reset
@@ -60,17 +60,17 @@ class ChipBringupHostConfig extends Config(
   //=============================
   // Setup the SerialTL side on the bringup device
   //=============================
-  new testchipip.WithSerialTLWidth(4) ++                                       // match width with the chip
+  new testchipip.serdes.WithSerialTLWidth(4) ++                                // match width with the chip
-  new testchipip.WithSerialTLMem(base = 0x0, size = 0x80000000L,               // accessible memory of the chip that doesn't come from the tethered host
+  new testchipip.serdes.WithSerialTLMem(base = 0x0, size = 0x80000000L,        // accessible memory of the chip that doesn't come from the tethered host
-                                 idBits = 4, isMainMemory = false) ++          // This assumes off-chip mem starts at 0x8000_0000
+                                        idBits = 4, isMainMemory = false) ++   // This assumes off-chip mem starts at 0x8000_0000
-  new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(75)) ++ // bringup board drives the clock for the serial-tl receiver on the chip, use 75MHz clock
+  new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(75)) ++ // bringup board drives the clock for the serial-tl receiver on the chip, use 75MHz clock
 
   //============================
   // Setup bus topology on the bringup system
   //============================
-  new testchipip.WithOffchipBusClient(SBUS,                                    // offchip bus hangs off the SBUS
+  new testchipip.soc.WithOffchipBusClient(SBUS,                                // offchip bus hangs off the SBUS
     blockRange = AddressSet.misaligned(0x80000000L, (BigInt(1) << 30) * 4)) ++ // offchip bus should not see the main memory of the testchip, since that can be accessed directly
-  new testchipip.WithOffchipBus ++                                             // offchip bus
+  new testchipip.soc.WithOffchipBus ++                                         // offchip bus
 
   //=============================
   // Set up memory on the bringup system
@@ -80,7 +80,7 @@ class ChipBringupHostConfig extends Config(
   //=============================
   // Generate the TSI-over-UART side of the bringup system
   //=============================
-  new testchipip.WithUARTTSIClient(initBaudRate = BigInt(921600)) ++           // nonstandard baud rate to improve performance
+  new testchipip.tsi.WithUARTTSIClient(initBaudRate = BigInt(921600)) ++       // nonstandard baud rate to improve performance
 
   //=============================
   // Set up clocks of the bringup system

generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala

@@ -19,14 +19,14 @@ class GB1MemoryRocketConfig extends Config(
 
 // DOC include start: mbusscratchpadrocket
 class MbusScratchpadOnlyRocketConfig extends Config(
-  new testchipip.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad
+  new testchipip.soc.WithMbusScratchpad(banks=2, partitions=2) ++ // add 2 partitions of 2 banks mbus backing scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++         // remove offchip mem port
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: mbusscratchpadrocket
 
 class SbusScratchpadRocketConfig extends Config(
-  new testchipip.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus scratchpad
+  new testchipip.soc.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus scratchpad
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 

generators/chipyard/src/main/scala/config/NoCoreConfigs.scala

@@ -4,8 +4,8 @@ import org.chipsalliance.cde.config.{Config}
 
 // A empty config with no cores. Useful for testing
 class NoCoresConfig extends Config(
-  new testchipip.WithNoBootAddrReg ++
+  new testchipip.boot.WithNoBootAddrReg ++
-  new testchipip.WithNoCustomBootPin ++
+  new testchipip.boot.WithNoCustomBootPin ++
   new chipyard.config.WithNoCLINT ++
   new chipyard.config.WithNoBootROM ++
   new chipyard.config.WithBroadcastManager ++

generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala

@@ -22,13 +22,13 @@ class SmallSPIFlashRocketConfig extends Config(
 
 class SimBlockDeviceRocketConfig extends Config(
   new chipyard.harness.WithSimBlockDevice ++                // drive block-device IOs with SimBlockDevice
-  new testchipip.WithBlockDevice ++                         // add block-device module to peripherybus
+  new testchipip.iceblk.WithBlockDevice ++                  // add block-device module to peripherybus
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
 class BlockDeviceModelRocketConfig extends Config(
   new chipyard.harness.WithBlockDeviceModel ++              // drive block-device IOs with a BlockDeviceModel
-  new testchipip.WithBlockDevice ++                         // add block-device module to periphery bus
+  new testchipip.iceblk.WithBlockDevice ++                  // add block-device module to periphery bus
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
@@ -53,10 +53,10 @@ class MMIORocketConfig extends Config(
 
 class LBWIFRocketConfig extends Config(
   new chipyard.config.WithOffchipBusFrequency(500) ++
-  new testchipip.WithOffchipBusClient(MBUS) ++
+  new testchipip.soc.WithOffchipBusClient(MBUS) ++
-  new testchipip.WithOffchipBus ++
+  new testchipip.soc.WithOffchipBus ++
-  new testchipip.WithSerialTLMem(isMainMemory=true) ++      // set lbwif memory base to DRAM_BASE, use as main memory
+  new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
-  new freechips.rocketchip.subsystem.WithNoMemPort ++       // remove AXI4 backing memory
+  new freechips.rocketchip.subsystem.WithNoMemPort ++         // remove AXI4 backing memory
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
@@ -69,10 +69,10 @@ class dmiRocketConfig extends Config(
 // DOC include end: DmiRocket
 
 class ManyPeripheralsRocketConfig extends Config(
-  new testchipip.WithBlockDevice ++                          // add block-device module to peripherybus
+  new testchipip.iceblk.WithBlockDevice ++                   // add block-device module to peripherybus
-  new testchipip.WithOffchipBusClient(MBUS) ++               // OBUS provides backing memory to the MBUS
+  new testchipip.soc.WithOffchipBusClient(MBUS) ++           // OBUS provides backing memory to the MBUS
-  new testchipip.WithOffchipBus ++                           // OBUS must exist for serial-tl to master off-chip memory
+  new testchipip.soc.WithOffchipBus ++                       // OBUS must exist for serial-tl to master off-chip memory
-  new testchipip.WithSerialTLMem(isMainMemory=true) ++       // set lbwif memory base to DRAM_BASE, use as main memory
+  new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
   new chipyard.harness.WithSimSPIFlashModel(true) ++         // add the SPI flash model in the harness (read-only)
   new chipyard.harness.WithSimBlockDevice ++                 // drive block-device IOs with SimBlockDevice
   new chipyard.config.WithSPIFlash ++                        // add the SPI flash controller
@@ -84,7 +84,7 @@ class ManyPeripheralsRocketConfig extends Config(
 
 class UARTTSIRocketConfig extends Config(
   new chipyard.harness.WithSerialTLTiedOff ++
-  new testchipip.WithUARTTSIClient ++
+  new testchipip.tsi.WithUARTTSIClient ++
   new chipyard.config.WithMemoryBusFrequency(10) ++
   new chipyard.config.WithFrontBusFrequency(10) ++
   new chipyard.config.WithPeripheryBusFrequency(10) ++

generators/chipyard/src/main/scala/config/SodorConfigs.scala

@@ -7,7 +7,7 @@ import org.chipsalliance.cde.config.{Config}
 class Sodor1StageConfig extends Config(
   // Create a Sodor 1-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++
-  new testchipip.WithSerialTLWidth(32) ++
+  new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -16,7 +16,7 @@ class Sodor1StageConfig extends Config(
 class Sodor2StageConfig extends Config(
   // Create a Sodor 2-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++
-  new testchipip.WithSerialTLWidth(32) ++
+  new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -25,7 +25,7 @@ class Sodor2StageConfig extends Config(
 class Sodor3StageConfig extends Config(
   // Create a Sodor 1-stage core with two ports
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++
-  new testchipip.WithSerialTLWidth(32) ++
+  new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -34,7 +34,7 @@ class Sodor3StageConfig extends Config(
 class Sodor3StageSinglePortConfig extends Config(
   // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter)
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++
-  new testchipip.WithSerialTLWidth(32) ++
+  new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -43,7 +43,7 @@ class Sodor3StageSinglePortConfig extends Config(
 class Sodor5StageConfig extends Config(
   // Create a Sodor 5-stage core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++
-  new testchipip.WithSerialTLWidth(32) ++
+  new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
@@ -52,7 +52,7 @@ class Sodor5StageConfig extends Config(
 class SodorUCodeConfig extends Config(
   // Construct a Sodor microcode-based single-bus core
   new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++
-  new testchipip.WithSerialTLWidth(32) ++
+  new testchipip.serdes.WithSerialTLWidth(32) ++
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++          // use no external memory
   new freechips.rocketchip.subsystem.WithNBanks(0) ++

generators/chipyard/src/main/scala/config/SpikeConfigs.scala

@@ -43,7 +43,7 @@ class SpikeUltraFastDevicesConfig extends Config(
   new chipyard.harness.WithSimBlockDevice ++
   new chipyard.harness.WithLoopbackNIC ++
   new icenet.WithIceNIC ++
-  new testchipip.WithBlockDevice ++
+  new testchipip.iceblk.WithBlockDevice ++
 
   new chipyard.WithSpikeTCM ++
   new chipyard.WithNSpikeCores(1) ++

generators/chipyard/src/main/scala/config/TracegenConfigs.scala

@@ -43,6 +43,6 @@ class NonBlockingTraceGenL2Config extends Config(
 
 class NonBlockingTraceGenL2RingConfig extends Config(
   new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
-  new testchipip.WithRingSystemBus ++
+  new testchipip.soc.WithRingSystemBus ++
   new freechips.rocketchip.subsystem.WithInclusiveCache ++
   new AbstractTraceGenConfig)

generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala

@@ -13,9 +13,7 @@ import freechips.rocketchip.tilelink.{HasTLBusParams}
 
 import chipyard._
 import chipyard.clocking._
-import testchipip.{OffchipBusKey}
+import testchipip.soc.{OffchipBusKey}
-
-import testchipip.{OffchipBusKey}
 
 // The default RocketChip BaseSubsystem drives its diplomatic clock graph
 // with the implicit clocks of Subsystem. Don't do that, instead we extend

generators/chipyard/src/main/scala/config/fragments/TileFragments.scala

@@ -11,7 +11,7 @@ import boom.common.{BoomTileAttachParams}
 import cva6.{CVA6TileAttachParams}
 import sodor.common.{SodorTileAttachParams}
 import ibex.{IbexTileAttachParams}
-import testchipip._
+import testchipip.cosim.{TracePortKey, TracePortParams}
 import barf.{TilePrefetchingMasterPortParams}
 
 class WithL2TLBs(entries: Int) extends Config((site, here, up) => {

generators/chipyard/src/main/scala/example/FlatChipTop.scala

@@ -14,7 +14,7 @@ import chipyard.harness.{BuildTop}
 import chipyard.clocking._
 import chipyard.iobinders._
 import barstools.iocell.chisel._
-import testchipip.{SerialTLKey}
+import testchipip.serdes.{SerialTLKey}
 
 class WithFlatChipTop extends Config((site, here, up) => {
   case BuildTop => (p: Parameters) => new FlatChipTop()(p)

generators/chipyard/src/main/scala/example/FlatTestHarness.scala

@@ -11,7 +11,10 @@ import freechips.rocketchip.util.{PlusArg}
 import freechips.rocketchip.subsystem.{CacheBlockBytes}
 import freechips.rocketchip.devices.debug.{SimJTAG}
 import freechips.rocketchip.jtag.{JTAGIO}
-import testchipip.{SerialTLKey, UARTAdapter, SimDRAM, TSIHarness, SimTSI}
+import testchipip.serdes.{SerialTLKey}
+import testchipip.uart.{UARTAdapter}
+import testchipip.dram.{SimDRAM}
+import testchipip.tsi.{TSIHarness, SimTSI}
 import chipyard.harness.{BuildTop}
 
 // A "flat" TestHarness that doesn't use IOBinders

generators/chipyard/src/main/scala/harness/HarnessBinders.scala

@@ -12,7 +12,14 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.jtag.{JTAGIO}
 import freechips.rocketchip.devices.debug.{SimJTAG}
 import barstools.iocell.chisel._
-import testchipip._
+import testchipip.dram.{SimDRAM}
+import testchipip.tsi.{SimTSI, SerialRAM, TSI, TSIIO}
+import testchipip.soc.{TestchipSimDTM}
+import testchipip.spi.{SimSPIFlashModel}
+import testchipip.uart.{UARTAdapter, UARTToSerial}
+import testchipip.serdes.{SerialWidthAdapter}
+import testchipip.iceblk.{SimBlockDevice, BlockDeviceModel}
+import testchipip.cosim.{SpikeCosim}
 import icenet.{NicLoopback, SimNetwork}
 import chipyard._
 import chipyard.clocking.{HasChipyardPRCI}

generators/chipyard/src/main/scala/iobinders/IOBinders.scala

@@ -23,7 +23,13 @@ import tracegen.{TraceGenSystemModuleImp}
 
 import barstools.iocell.chisel._
 
-import testchipip._
+import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey}
+import testchipip.spi.{SPIChipIO}
+import testchipip.boot.{CanHavePeripheryCustomBootPin}
+import testchipip.util.{ClockedIO}
+import testchipip.iceblk.{CanHavePeripheryBlockDevice, BlockDeviceKey, BlockDeviceIO}
+import testchipip.cosim.{CanHaveTraceIOModuleImp, TraceOutputTop, SpikeCosimConfig}
+import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO}
 import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
 import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule}
 

generators/chipyard/src/main/scala/iobinders/Ports.scala

@@ -4,9 +4,13 @@ import chisel3._
 import chisel3.experimental.{Analog}
 import sifive.blocks.devices.uart.{UARTPortIO}
 import sifive.blocks.devices.spi.{SPIFlashParams, SPIPortIO}
-import sifive.blocks.devices.i2c.{I2CPort}
 import sifive.blocks.devices.gpio.{GPIOPortIO}
-import testchipip._
+import testchipip.util.{ClockedIO}
+import testchipip.serdes.{TLSerdesser, SerialIO, SerialTLParams}
+import testchipip.spi.{SPIChipIO}
+import testchipip.cosim.{TraceOutputTop, SpikeCosimConfig}
+import testchipip.iceblk.{BlockDeviceIO, BlockDeviceConfig}
+import testchipip.tsi.{UARTTSIIO}
 import icenet.{NICIOvonly, NICConfig}
 import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4EdgeParameters}

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -15,7 +15,7 @@ import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 import sifive.blocks.devices.uart._
 
-import testchipip._
+import testchipip.tsi.{SerialRAM}
 import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
 
 import junctions.{NastiKey, NastiParameters}

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -13,7 +13,8 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams}
 import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
 import freechips.rocketchip.diplomacy.{LazyModule, AsynchronousCrossing}
-import testchipip.{BlockDeviceKey, BlockDeviceConfig, TracePortKey, TracePortParams}
+import testchipip.iceblk.{BlockDeviceKey, BlockDeviceConfig}
+import testchipip.cosim.{TracePortKey, TracePortParams}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
 import scala.math.{min, max}
 
@@ -101,7 +102,7 @@ class WithFireSimDesignTweaks extends Config(
   // Required: Bake in the default FASED memory model
   new WithDefaultMemModel ++
   // Optional: reduce the width of the Serial TL interface
-  new testchipip.WithSerialTLWidth(4) ++
+  new testchipip.serdes.WithSerialTLWidth(4) ++
   // Required*: Scale default baud rate with periphery bus frequency
   new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
   // Optional: Adds IO to attach tracerV bridges
@@ -109,7 +110,7 @@ class WithFireSimDesignTweaks extends Config(
   // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 64 GiB on F1)
   new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++
   // Optional: Removing this will require using an initramfs under linux
-  new testchipip.WithBlockDevice
+  new testchipip.iceblk.WithBlockDevice
 )
 
 // Tweaks to modify target clock frequencies / crossings to legacy firesim defaults
@@ -151,7 +152,7 @@ class WithFireSimConfigTweaks extends Config(
 class WithMinimalFireSimHighPerfConfigTweaks extends Config(
   new WithFireSimHighPerfClocking ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++
-  new testchipip.WithMbusScratchpad ++
+  new testchipip.soc.WithMbusScratchpad ++
   new WithMinimalFireSimDesignTweaks
 )
 
@@ -161,8 +162,8 @@ class WithMinimalFireSimHighPerfConfigTweaks extends Config(
 class WithMinimalAndBlockDeviceFireSimHighPerfConfigTweaks extends Config(
   new WithFireSimHighPerfClocking ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++ // removes mem port for FASEDBridge to match against
-  new testchipip.WithMbusScratchpad ++ // adds backing scratchpad for memory to replace FASED model
+  new testchipip.soc.WithMbusScratchpad ++ // adds backing scratchpad for memory to replace FASED model
-  new testchipip.WithBlockDevice(true) ++ // add in block device
+  new testchipip.iceblk.WithBlockDevice(true) ++ // add in block device
   new WithMinimalFireSimDesignTweaks
 )
 
@@ -257,11 +258,11 @@ class FireSimSmallSystemConfig extends Config(
   new WithoutClockGating ++
   new WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
-  new testchipip.WithSerialTL(Seq(testchipip.SerialTLParams(
+  new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams(
-    client = Some(testchipip.SerialTLClientParams(idBits = 4)),
+    client = Some(testchipip.serdes.SerialTLClientParams(idBits = 4)),
     width = 32
   ))) ++
-  new testchipip.WithBlockDevice ++
+  new testchipip.iceblk.WithBlockDevice ++
   new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
   new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++
   new chipyard.RocketConfig)
@@ -339,7 +340,7 @@ class FireSim16LargeBoomConfig extends Config(
 class FireSimNoMemPortConfig extends Config(
   new WithDefaultFireSimBridges ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++
-  new testchipip.WithMbusScratchpad ++
+  new testchipip.soc.WithMbusScratchpad ++
   new WithFireSimConfigTweaks ++
   new chipyard.RocketConfig)
 

variables.mk

@@ -97,7 +97,7 @@ ifeq ($(SUB_PROJECT),testchipip)
 	VLOG_MODEL        ?= $(MODEL)
 	MODEL_PACKAGE     ?= chipyard.unittest
 	CONFIG            ?= TestChipUnitTestConfig
-	CONFIG_PACKAGE    ?= testchipip
+	CONFIG_PACKAGE    ?= testchipip.test
 	GENERATOR_PACKAGE ?= chipyard
 	TB                ?= TestDriver
 	TOP               ?= UnitTestSuite