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[clocking] Fix FireSim clock look up

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This commit is contained in:
David Biancolin
2020-09-25 10:05:28 -07:00
parent 1b3514f95f
commit 67145c6ccd
1 changed files with 2 additions and 2 deletions
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4
generators/firechip/src/main/scala/FireSim.scala
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@@ -68,8 +68,8 @@ class ClockBridgeInstantiator {
val clockBridge = Module(new RationalClockBridge(distinct)) val clockBridge = Module(new RationalClockBridge(distinct))
val cbVecTuples = distinct.zip(clockBridge.io.clocks) val cbVecTuples = distinct.zip(clockBridge.io.clocks)
val outputWire = Wire(RecordMap(allClocks.map { c => (c.name, Clock()) }:_*)) val outputWire = Wire(RecordMap(simplified.map { c => (c.name, Clock()) }:_*))
for (parameter <- allClocks) { for (parameter <- simplified) {
val (_, cbClockField) = cbVecTuples.find(_._1.equalFrequency(parameter)).get val (_, cbClockField) = cbVecTuples.find(_._1.equalFrequency(parameter)).get
outputWire(parameter.name).get := cbClockField outputWire(parameter.name).get := cbClockField
} }