[clocking] Fix FireSim clock look up

2020-09-25 10:05:28 -07:00
parent 1b3514f95f
commit 67145c6ccd
1 changed files with 2 additions and 2 deletions
--- a/generators/firechip/src/main/scala/FireSim.scala
+++ b/generators/firechip/src/main/scala/FireSim.scala
@@ -68,8 +68,8 @@ class ClockBridgeInstantiator {

      val clockBridge = Module(new RationalClockBridge(distinct))
      val cbVecTuples = distinct.zip(clockBridge.io.clocks)
-      val outputWire = Wire(RecordMap(allClocks.map { c => (c.name, Clock()) }:_*))
-      for (parameter <- allClocks) {
+      val outputWire = Wire(RecordMap(simplified.map { c => (c.name, Clock()) }:_*))
+      for (parameter <- simplified) {
        val (_, cbClockField) = cbVecTuples.find(_._1.equalFrequency(parameter)).get
        outputWire(parameter.name).get := cbClockField
      }